Michael J. Metzger

Array ( [id] => 13511897 [patent_doc_number] => 20180307491 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-25 [patent_title] => EARLY PREDICATE LOOK-UP [patent_app_type] => utility [patent_app_number] => 15/493492 [patent_app_country] => US [patent_app_date] => 2017-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9248 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15493492 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15106289 [patent_doc_number] => 10474469 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-12 [patent_title] => Apparatus and method for determining a recovery point from which to resume instruction execution following handling of an unexpected change in instruction flow [patent_app_type] => utility [patent_app_number] => 15/485507 [patent_app_country] => US [patent_app_date] => 2017-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 19 [patent_no_of_words] => 13785 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15485507 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13483067 [patent_doc_number] => 20180293076 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-11 [patent_title] => BRANCH PREDICTOR SELECTION MANAGEMENT [patent_app_type] => utility [patent_app_number] => 15/479326 [patent_app_country] => US [patent_app_date] => 2017-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12613 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15479326 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13467137 [patent_doc_number] => 20180285111 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-04 [patent_title] => METHOD OF DETECTING REPETITION OF AN OUT-OF-ORDER EXECUTION SCHEDULE, APPARATUS AND COMPUTER-READABLE MEDIUM [patent_app_type] => utility [patent_app_number] => 15/478552 [patent_app_country] => US [patent_app_date] => 2017-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8320 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15478552 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11996167 [patent_doc_number] => 20170300322 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-19 [patent_title] => 'ARITHMETIC PROCESSING DEVICE, METHOD, AND SYSTEM' [patent_app_type] => utility [patent_app_number] => 15/478528 [patent_app_country] => US [patent_app_date] => 2017-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5782 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15478528 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13186121 [patent_doc_number] => 10108581 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-10-23 [patent_title] => Vector reduction processor [patent_app_type] => utility [patent_app_number] => 15/477791 [patent_app_country] => US [patent_app_date] => 2017-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 14561 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15477791 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13467145 [patent_doc_number] => 20180285115 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-04 [patent_title] => MISPREDICTION-TRIGGERED LOCAL HISTORY-BASED BRANCH PREDICTION [patent_app_type] => utility [patent_app_number] => 15/477064 [patent_app_country] => US [patent_app_date] => 2017-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8052 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15477064 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13467125 [patent_doc_number] => 20180285105 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-04 [patent_title] => EFFICIENT RANGE-BASED MEMORY WRITEBACK TO IMPROVE HOST TO DEVICE COMMMUNICATION FOR OPTIMAL POWER AND PERFORMANCE [patent_app_type] => utility [patent_app_number] => 15/476302 [patent_app_country] => US [patent_app_date] => 2017-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10972 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15476302 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15399041 [patent_doc_number] => 10540177 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-21 [patent_title] => Efficient zero-based decompression [patent_app_type] => utility [patent_app_number] => 15/438712 [patent_app_country] => US [patent_app_date] => 2017-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 23 [patent_no_of_words] => 16050 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15438712 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11838624 [patent_doc_number] => 20170220344 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-03 [patent_title] => 'STOCHASTIC ROUNDING FLOATING-POINT ADD INSTRUCTION USING ENTROPY FROM A REGISTER' [patent_app_type] => utility [patent_app_number] => 15/432551 [patent_app_country] => US [patent_app_date] => 2017-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7489 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15432551 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14982311 [patent_doc_number] => 10445066 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-15 [patent_title] => Stochastic rounding floating-point multiply instruction using entropy from a register [patent_app_type] => utility [patent_app_number] => 15/432462 [patent_app_country] => US [patent_app_date] => 2017-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 6894 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15432462 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11651448 [patent_doc_number] => 20170147348 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-25 [patent_title] => 'METHOD AND APPARATUS TO PROCESS SHA-2 SECURE HASHING ALGORITHM' [patent_app_type] => utility [patent_app_number] => 15/396563 [patent_app_country] => US [patent_app_date] => 2016-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 21272 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15396563 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11570518 [patent_doc_number] => 20170109162 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-20 [patent_title] => 'METHOD AND APPARATUS TO PROCESS SHA-2 SECURE HASHING ALGORITHM' [patent_app_type] => utility [patent_app_number] => 15/396572 [patent_app_country] => US [patent_app_date] => 2016-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 21232 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15396572 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11651439 [patent_doc_number] => 20170147340 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-25 [patent_title] => 'METHOD AND APPARATUS TO PROCESS SHA-2 SECURE HASHING ALGORITHM' [patent_app_type] => utility [patent_app_number] => 15/396568 [patent_app_country] => US [patent_app_date] => 2016-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 21349 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15396568 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11651441 [patent_doc_number] => 20170147342 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-25 [patent_title] => 'METHOD AND APPARATUS TO PROCESS SHA-2 SECURE HASHING ALGORITHM' [patent_app_type] => utility [patent_app_number] => 15/396576 [patent_app_country] => US [patent_app_date] => 2016-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 21275 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15396576 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11651442 [patent_doc_number] => 20170147343 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-25 [patent_title] => 'METHOD AND APPARATUS TO PROCESS SHA-2 SECURE HASHING ALGORITHM' [patent_app_type] => utility [patent_app_number] => 15/396578 [patent_app_country] => US [patent_app_date] => 2016-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 21263 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15396578 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11651440 [patent_doc_number] => 20170147341 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-25 [patent_title] => 'METHOD AND APPARATUS TO PROCESS SHA-2 SECURE HASHING ALGORITHM' [patent_app_type] => utility [patent_app_number] => 15/396574 [patent_app_country] => US [patent_app_date] => 2016-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 21286 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15396574 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12891658 [patent_doc_number] => 20180189061 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-05 [patent_title] => SYSTEMS, APPARATUSES, AND METHODS FOR BROADCAST ARITHMETIC OPERATIONS [patent_app_type] => utility [patent_app_number] => 15/396111 [patent_app_country] => US [patent_app_date] => 2016-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18656 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15396111 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16802104 [patent_doc_number] => 10997048 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-04 [patent_title] => Apparatus and method for multithreading-aware performance monitoring events [patent_app_type] => utility [patent_app_number] => 15/395903 [patent_app_country] => US [patent_app_date] => 2016-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 23 [patent_no_of_words] => 16421 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15395903 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12868669 [patent_doc_number] => 20180181398 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-28 [patent_title] => APPARATUS AND METHODS OF DECOMPOSING LOOPS TO IMPROVE PERFORMANCE AND POWER EFFICIENCY [patent_app_type] => utility [patent_app_number] => 15/392626 [patent_app_country] => US [patent_app_date] => 2016-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20711 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15392626 [rel_patent_id] =>[rel_patent_doc_number] =>)