Search

Michael J. Metzger

Examiner (ID: 19567, Phone: (571)272-3105 , Office: P/2182 )

Most Active Art Unit
2182
Art Unit(s)
2182, 2183
Total Applications
577
Issued Applications
477
Pending Applications
65
Abandoned Applications
48

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16065003 [patent_doc_number] => 10691451 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-23 [patent_title] => Processor instructions to accelerate FEC encoding and decoding [patent_app_type] => utility [patent_app_number] => 15/390910 [patent_app_country] => US [patent_app_date] => 2016-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 13668 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15390910 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/390910
Processor instructions to accelerate FEC encoding and decoding Dec 26, 2016 Issued
Array ( [id] => 14704215 [patent_doc_number] => 10379854 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-13 [patent_title] => Processor instructions for determining two minimum and two maximum values [patent_app_type] => utility [patent_app_number] => 15/387823 [patent_app_country] => US [patent_app_date] => 2016-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 13351 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15387823 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/387823
Processor instructions for determining two minimum and two maximum values Dec 21, 2016 Issued
Array ( [id] => 15472665 [patent_doc_number] => 10552207 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-04 [patent_title] => Systems and methods for multi-architecture computing including program stack translation [patent_app_type] => utility [patent_app_number] => 15/386990 [patent_app_country] => US [patent_app_date] => 2016-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 19199 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15386990 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/386990
Systems and methods for multi-architecture computing including program stack translation Dec 20, 2016 Issued
Array ( [id] => 12845071 [patent_doc_number] => 20180173530 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-21 [patent_title] => SYSTEMS AND METHODS FOR MULTI-ARCHITECTURE COMPUTING [patent_app_type] => utility [patent_app_number] => 15/387106 [patent_app_country] => US [patent_app_date] => 2016-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19200 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15387106 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/387106
SYSTEMS AND METHODS FOR MULTI-ARCHITECTURE COMPUTING Dec 20, 2016 Abandoned
Array ( [id] => 12845503 [patent_doc_number] => 20180173674 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-21 [patent_title] => SYSTEMS AND METHODS FOR MULTI-ARCHITECTURE COMPUTING [patent_app_type] => utility [patent_app_number] => 15/386833 [patent_app_country] => US [patent_app_date] => 2016-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19200 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15386833 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/386833
Computing devices and server systems with processing cores having different instruction set architectures Dec 20, 2016 Issued
Array ( [id] => 11445140 [patent_doc_number] => 20170046161 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-16 [patent_title] => 'BRANCH PREDICTION USING MULTIPLE VERSIONS OF HISTORY DATA' [patent_app_type] => utility [patent_app_number] => 15/342139 [patent_app_country] => US [patent_app_date] => 2016-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4198 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15342139 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/342139
Branch prediction using multiple versions of history data Nov 2, 2016 Issued
Array ( [id] => 11445141 [patent_doc_number] => 20170046162 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-16 [patent_title] => 'BRANCH PREDICTION USING MULTIPLE VERSIONS OF HISTORY DATA' [patent_app_type] => utility [patent_app_number] => 15/342141 [patent_app_country] => US [patent_app_date] => 2016-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4198 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15342141 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/342141
Branch prediction using multiple versions of history data Nov 2, 2016 Issued
Array ( [id] => 12688102 [patent_doc_number] => 20180121200 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-03 [patent_title] => HYBRID LOOKAHEAD BRANCH TARGET CACHE [patent_app_type] => utility [patent_app_number] => 15/340106 [patent_app_country] => US [patent_app_date] => 2016-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9279 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15340106 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/340106
Hybrid lookahead branch target cache Oct 31, 2016 Issued
Array ( [id] => 12039429 [patent_doc_number] => 09817662 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-11-14 [patent_title] => 'Apparatus for calculating and retaining a bound on error during floating point operations and methods thereof' [patent_app_type] => utility [patent_app_number] => 15/331901 [patent_app_country] => US [patent_app_date] => 2016-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 15716 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 412 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15331901 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/331901
Apparatus for calculating and retaining a bound on error during floating point operations and methods thereof Oct 22, 2016 Issued
Array ( [id] => 11846572 [patent_doc_number] => 09734126 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-08-15 [patent_title] => 'Post-silicon configurable instruction behavior based on input operands' [patent_app_type] => utility [patent_app_number] => 15/289388 [patent_app_country] => US [patent_app_date] => 2016-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6492 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15289388 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/289388
Post-silicon configurable instruction behavior based on input operands Oct 9, 2016 Issued
Array ( [id] => 12611760 [patent_doc_number] => 20180095750 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-05 [patent_title] => HARDWARE ACCELERATORS AND METHODS FOR OFFLOAD OPERATIONS [patent_app_type] => utility [patent_app_number] => 15/282372 [patent_app_country] => US [patent_app_date] => 2016-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 28034 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15282372 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/282372
Hardware accelerators and methods for offload operations Sep 29, 2016 Issued
Array ( [id] => 11530950 [patent_doc_number] => 20170090928 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-30 [patent_title] => 'VECTOR PERMUTATION CIRCUIT AND VECTOR PROCESSOR' [patent_app_type] => utility [patent_app_number] => 15/280388 [patent_app_country] => US [patent_app_date] => 2016-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 17736 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15280388 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/280388
Vector permutation circuit and vector processor Sep 28, 2016 Issued
Array ( [id] => 14489333 [patent_doc_number] => 10331454 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-25 [patent_title] => System and method for load balancing in out-of-order clustered decoding [patent_app_type] => utility [patent_app_number] => 15/280460 [patent_app_country] => US [patent_app_date] => 2016-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 40 [patent_no_of_words] => 38215 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15280460 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/280460
System and method for load balancing in out-of-order clustered decoding Sep 28, 2016 Issued
Array ( [id] => 11550389 [patent_doc_number] => 09619237 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-11 [patent_title] => 'Speculative branch handling for transaction abort' [patent_app_type] => utility [patent_app_number] => 15/244741 [patent_app_country] => US [patent_app_date] => 2016-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3765 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 310 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15244741 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/244741
Speculative branch handling for transaction abort Aug 22, 2016 Issued
Array ( [id] => 11326957 [patent_doc_number] => 20160357570 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-08 [patent_title] => 'RESTRICTED INSTRUCTIONS IN TRANSACTIONAL EXECUTION' [patent_app_type] => utility [patent_app_number] => 15/238270 [patent_app_country] => US [patent_app_date] => 2016-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 30573 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15238270 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/238270
Restricted instructions in transactional execution Aug 15, 2016 Issued
Array ( [id] => 12100988 [patent_doc_number] => 09858082 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-02 [patent_title] => 'Restricted instructions in transactional execution' [patent_app_type] => utility [patent_app_number] => 15/238306 [patent_app_country] => US [patent_app_date] => 2016-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 29 [patent_no_of_words] => 30560 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15238306 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/238306
Restricted instructions in transactional execution Aug 15, 2016 Issued
Array ( [id] => 11117023 [patent_doc_number] => 20160313998 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-27 [patent_title] => 'INSTRUCTION PREDICATION USING UNUSED DATAPATH FACILITIES' [patent_app_type] => utility [patent_app_number] => 15/202559 [patent_app_country] => US [patent_app_date] => 2016-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10536 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15202559 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/202559
Instruction predication using unused datapath facilities Jul 4, 2016 Issued
Array ( [id] => 16278822 [patent_doc_number] => 10761853 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-01 [patent_title] => Extending data range addressing [patent_app_type] => utility [patent_app_number] => 15/194666 [patent_app_country] => US [patent_app_date] => 2016-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 25 [patent_no_of_words] => 11350 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 329 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15194666 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/194666
Extending data range addressing Jun 27, 2016 Issued
Array ( [id] => 11109748 [patent_doc_number] => 20160306718 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-20 [patent_title] => 'RANDOMIZED TESTING WITHIN TRANSACTIONAL EXECUTION' [patent_app_type] => utility [patent_app_number] => 15/192565 [patent_app_country] => US [patent_app_date] => 2016-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 30462 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15192565 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/192565
Randomized testing within transactional execution Jun 23, 2016 Issued
Array ( [id] => 11095008 [patent_doc_number] => 20160291976 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-06 [patent_title] => 'SPECULATIVE LOAD ISSUE' [patent_app_type] => utility [patent_app_number] => 15/183365 [patent_app_country] => US [patent_app_date] => 2016-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10903 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15183365 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/183365
Speculative load issue Jun 14, 2016 Issued
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