Search

Michael J. Metzger

Examiner (ID: 19567, Phone: (571)272-3105 , Office: P/2182 )

Most Active Art Unit
2182
Art Unit(s)
2182, 2183
Total Applications
577
Issued Applications
477
Pending Applications
65
Abandoned Applications
48

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16032265 [patent_doc_number] => 10678551 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-09 [patent_title] => Operation of a multi-slice processor implementing tagged geometric history length (TAGE) branch prediction [patent_app_type] => utility [patent_app_number] => 15/163987 [patent_app_country] => US [patent_app_date] => 2016-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5939 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15163987 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/163987
Operation of a multi-slice processor implementing tagged geometric history length (TAGE) branch prediction May 24, 2016 Issued
Array ( [id] => 11069943 [patent_doc_number] => 20160266907 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-15 [patent_title] => 'SAVING/RESTORING SELECTED REGISTERS IN TRANSACTIONAL PROCESSING' [patent_app_type] => utility [patent_app_number] => 15/159905 [patent_app_country] => US [patent_app_date] => 2016-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 29082 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15159905 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/159905
Saving/restoring selected registers in transactional processing May 19, 2016 Issued
Array ( [id] => 11042506 [patent_doc_number] => 20160239462 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-18 [patent_title] => 'MULTI-LEVEL HIERARCHICAL ROUTING MATRICES FOR PATTERN-RECOGNITION PROCESSORS' [patent_app_type] => utility [patent_app_number] => 15/137877 [patent_app_country] => US [patent_app_date] => 2016-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 10064 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15137877 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/137877
Multi-level hierarchical routing matrices for pattern-recognition processors Apr 24, 2016 Issued
Array ( [id] => 16145035 [patent_doc_number] => 10705587 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-07 [patent_title] => Mode switching in dependence upon a number of active threads [patent_app_type] => utility [patent_app_number] => 15/133329 [patent_app_country] => US [patent_app_date] => 2016-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3511 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15133329 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/133329
Mode switching in dependence upon a number of active threads Apr 19, 2016 Issued
Array ( [id] => 11996181 [patent_doc_number] => 20170300336 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-19 [patent_title] => 'FPSCR STICKY BIT HANDLING FOR OUT OF ORDER INSTRUCTION EXECUTION' [patent_app_type] => utility [patent_app_number] => 15/131502 [patent_app_country] => US [patent_app_date] => 2016-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6143 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15131502 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/131502
FPSCR STICKY BIT HANDLING FOR OUT OF ORDER INSTRUCTION EXECUTION Apr 17, 2016 Abandoned
Array ( [id] => 11278685 [patent_doc_number] => 09495164 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-15 [patent_title] => 'Branch prediction using multiple versions of history data' [patent_app_type] => utility [patent_app_number] => 15/096407 [patent_app_country] => US [patent_app_date] => 2016-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4198 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 525 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15096407 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/096407
Branch prediction using multiple versions of history data Apr 11, 2016 Issued
Array ( [id] => 11973385 [patent_doc_number] => 20170277538 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-28 [patent_title] => 'SPECULATIVE MULTI-THREADING TRACE PREDICTION' [patent_app_type] => utility [patent_app_number] => 15/079181 [patent_app_country] => US [patent_app_date] => 2016-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7323 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15079181 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/079181
SPECULATIVE MULTI-THREADING TRACE PREDICTION Mar 23, 2016 Abandoned
Array ( [id] => 11973389 [patent_doc_number] => 20170277543 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-28 [patent_title] => 'OPERATION OF A MULTI-SLICE PROCESSOR WITH DYNAMIC CANCELING OF PARTIAL LOADS' [patent_app_type] => utility [patent_app_number] => 15/079452 [patent_app_country] => US [patent_app_date] => 2016-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6740 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15079452 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/079452
Operation of a multi-slice processor with dynamic canceling of partial loads Mar 23, 2016 Issued
Array ( [id] => 11086270 [patent_doc_number] => 20160283235 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-29 [patent_title] => 'CONTROLLING DATA FLOW BETWEEN PROCESSORS IN A PROCESSING SYSTEM' [patent_app_type] => utility [patent_app_number] => 15/079269 [patent_app_country] => US [patent_app_date] => 2016-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 12478 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15079269 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/079269
Controlling register bank access between program and dedicated processors in a processing system Mar 23, 2016 Issued
Array ( [id] => 14330637 [patent_doc_number] => 10296337 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-21 [patent_title] => Preventing premature reads from a general purpose register [patent_app_type] => utility [patent_app_number] => 15/075771 [patent_app_country] => US [patent_app_date] => 2016-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8137 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15075771 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/075771
Preventing premature reads from a general purpose register Mar 20, 2016 Issued
Array ( [id] => 11516261 [patent_doc_number] => 20170083335 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-23 [patent_title] => 'BROADCAST CHANNEL ARCHITECTURES FOR BLOCK-BASED PROCESSORS' [patent_app_type] => utility [patent_app_number] => 15/074938 [patent_app_country] => US [patent_app_date] => 2016-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 20158 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15074938 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/074938
Broadcast channel architectures for block-based processors Mar 17, 2016 Issued
Array ( [id] => 11516247 [patent_doc_number] => 20170083322 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-23 [patent_title] => 'MULTIMODAL TARGETS IN A BLOCK-BASED PROCESSOR' [patent_app_type] => utility [patent_app_number] => 15/073365 [patent_app_country] => US [patent_app_date] => 2016-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 15921 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15073365 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/073365
Multimodal targets in a block-based processor Mar 16, 2016 Issued
Array ( [id] => 13767291 [patent_doc_number] => 10175987 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-08 [patent_title] => Instruction prefetching in a computer processor using a prefetch prediction vector [patent_app_type] => utility [patent_app_number] => 15/072717 [patent_app_country] => US [patent_app_date] => 2016-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6282 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15072717 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/072717
Instruction prefetching in a computer processor using a prefetch prediction vector Mar 16, 2016 Issued
Array ( [id] => 11516257 [patent_doc_number] => 20170083331 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-23 [patent_title] => 'MEMORY SYNCHRONIZATION IN BLOCK-BASED PROCESSORS' [patent_app_type] => utility [patent_app_number] => 15/072031 [patent_app_country] => US [patent_app_date] => 2016-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 17835 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15072031 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/072031
MEMORY SYNCHRONIZATION IN BLOCK-BASED PROCESSORS Mar 15, 2016 Abandoned
Array ( [id] => 11226654 [patent_doc_number] => 09454377 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-27 [patent_title] => 'Speculative branch handling for transaction abort' [patent_app_type] => utility [patent_app_number] => 15/052090 [patent_app_country] => US [patent_app_date] => 2016-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3707 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15052090 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/052090
Speculative branch handling for transaction abort Feb 23, 2016 Issued
Array ( [id] => 11838620 [patent_doc_number] => 20170220341 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-03 [patent_title] => 'STOCHASTIC ROUNDING FLOATING-POINT MULTIPLY INSTRUCTION USING ENTROPY FROM A REGISTER' [patent_app_type] => utility [patent_app_number] => 15/009372 [patent_app_country] => US [patent_app_date] => 2016-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7059 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15009372 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/009372
Stochastic rounding floating-point multiply instruction using entropy from a register Jan 27, 2016 Issued
Array ( [id] => 11838622 [patent_doc_number] => 20170220342 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-03 [patent_title] => 'STOCHASTIC ROUNDING FLOATING-POINT ADD INSTRUCTION USING ENTROPY FROM A REGISTER' [patent_app_type] => utility [patent_app_number] => 15/009397 [patent_app_country] => US [patent_app_date] => 2016-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7452 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15009397 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/009397
Stochastic rounding floating-point add instruction using entropy from a register Jan 27, 2016 Issued
Array ( [id] => 11745667 [patent_doc_number] => 20170199741 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-13 [patent_title] => 'INSTRUCTION TRANSFER CONTROL USING PROGRAM COUNTERS' [patent_app_type] => utility [patent_app_number] => 14/994796 [patent_app_country] => US [patent_app_date] => 2016-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6004 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14994796 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/994796
Processing instruction control transfer instructions Jan 12, 2016 Issued
Array ( [id] => 13919673 [patent_doc_number] => 10203959 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-02-12 [patent_title] => Subroutine power optimiztion [patent_app_type] => utility [patent_app_number] => 14/993627 [patent_app_country] => US [patent_app_date] => 2016-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6341 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14993627 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/993627
Subroutine power optimiztion Jan 11, 2016 Issued
Array ( [id] => 12120945 [patent_doc_number] => 20180004530 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-04 [patent_title] => 'ADVANCED PROCESSOR ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 15/535697 [patent_app_country] => US [patent_app_date] => 2015-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 31410 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15535697 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/535697
Advanced processor architecture Dec 12, 2015 Issued
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