Michael J. Metzger

Array ( [id] => 11245270 [patent_doc_number] => 09471313 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-10-18 [patent_title] => 'Flushing speculative instruction processing' [patent_app_type] => utility [patent_app_number] => 14/952020 [patent_app_country] => US [patent_app_date] => 2015-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 17196 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14952020 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10824591 [patent_doc_number] => 20160170757 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-16 [patent_title] => 'PROGRAMMABLE LOAD REPLAY PRECLUDING MECHANISM' [patent_app_type] => utility [patent_app_number] => 14/950439 [patent_app_country] => US [patent_app_date] => 2015-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10786 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14950439 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10824593 [patent_doc_number] => 20160170759 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-16 [patent_title] => 'MECHANISM TO PRECLUDE SHARED RAM-DEPENDENT LOAD REPLAYS IN AN OUT-OF-ORDER PROCESSOR' [patent_app_type] => utility [patent_app_number] => 14/950555 [patent_app_country] => US [patent_app_date] => 2015-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10799 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14950555 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13143557 [patent_doc_number] => 10089112 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-02 [patent_title] => Mechanism to preclude load replays dependent on fuse array access in an out-of-order processor [patent_app_type] => utility [patent_app_number] => 14/950283 [patent_app_country] => US [patent_app_date] => 2015-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 10309 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 398 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14950283 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13143101 [patent_doc_number] => 10088881 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-02 [patent_title] => Mechanism to preclude I/O-dependent load replays in an out-of-order processor [patent_app_type] => utility [patent_app_number] => 14/950306 [patent_app_country] => US [patent_app_date] => 2015-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 10257 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 368 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14950306 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10824597 [patent_doc_number] => 20160170763 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-16 [patent_title] => 'APPARATUS AND METHOD TO PRECLUDE LOAD REPLAYS DEPENDENT ON WRITE COMBINING MEMORY SPACE ACCESS IN AN OUT-OF-ORDER PROCESSOR' [patent_app_type] => utility [patent_app_number] => 14/950684 [patent_app_country] => US [patent_app_date] => 2015-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10787 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14950684 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13226541 [patent_doc_number] => 10127046 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-13 [patent_title] => Mechanism to preclude uncacheable-dependent load replays in out-of-order processor [patent_app_type] => utility [patent_app_number] => 14/950331 [patent_app_country] => US [patent_app_date] => 2015-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 10258 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 400 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14950331 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10824595 [patent_doc_number] => 20160170761 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-16 [patent_title] => 'MECHANISM TO PRECLUDE LOAD REPLAYS DEPENDENT ON OFF-DIE CONTROL ELEMENT ACCESS IN AN OUT-OF-ORDER PROCESSOR' [patent_app_type] => utility [patent_app_number] => 14/950615 [patent_app_country] => US [patent_app_date] => 2015-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10727 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14950615 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10824594 [patent_doc_number] => 20160170760 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-16 [patent_title] => 'APPARATUS AND METHOD TO PRECLUDE NON-CORE CACHE-DEPENDENT LOAD REPLAYS IN AN OUT-OF-ORDER PROCESSOR' [patent_app_type] => utility [patent_app_number] => 14/950582 [patent_app_country] => US [patent_app_date] => 2015-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10807 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14950582 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13268909 [patent_doc_number] => 10146539 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-04 [patent_title] => Load replay precluding mechanism [patent_app_type] => utility [patent_app_number] => 14/950365 [patent_app_country] => US [patent_app_date] => 2015-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 10235 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 388 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14950365 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10824598 [patent_doc_number] => 20160170764 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-16 [patent_title] => 'APPARATUS AND METHOD FOR PROGRAMMABLE LOAD REPLAY PRECLUSION' [patent_app_type] => utility [patent_app_number] => 14/950713 [patent_app_country] => US [patent_app_date] => 2015-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10838 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14950713 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10824590 [patent_doc_number] => 20160170756 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-16 [patent_title] => 'MECHANISM TO PRECLUDE LOAD REPLAYS DEPENDENT ON LONG LOAD CYCLES IN AN OUT-OF-ORDER PROCESSOR' [patent_app_type] => utility [patent_app_number] => 14/950415 [patent_app_country] => US [patent_app_date] => 2015-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10747 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14950415 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11516358 [patent_doc_number] => 20170083431 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-23 [patent_title] => 'DEBUG SUPPORT FOR BLOCK-BASED PROCESSOR' [patent_app_type] => utility [patent_app_number] => 14/942557 [patent_app_country] => US [patent_app_date] => 2015-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 22512 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14942557 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11516267 [patent_doc_number] => 20170083341 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-23 [patent_title] => 'SEGMENTED INSTRUCTION BLOCK' [patent_app_type] => utility [patent_app_number] => 14/942345 [patent_app_country] => US [patent_app_date] => 2015-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 22716 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14942345 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16278821 [patent_doc_number] => 10761852 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-01 [patent_title] => Extending data range addressing [patent_app_type] => utility [patent_app_number] => 14/871959 [patent_app_country] => US [patent_app_date] => 2015-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 25 [patent_no_of_words] => 11378 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 352 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14871959 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12173771 [patent_doc_number] => 09891914 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-13 [patent_title] => 'Method and apparatus for performing an efficient scatter' [patent_app_type] => utility [patent_app_number] => 14/684150 [patent_app_country] => US [patent_app_date] => 2015-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 14963 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14684150 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11042346 [patent_doc_number] => 20160239302 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-18 [patent_title] => 'DYNAMIC WAVEFRONT CREATION FOR PROCESSING UNITS USING A HYBRID COMPACTOR' [patent_app_type] => utility [patent_app_number] => 14/682971 [patent_app_country] => US [patent_app_date] => 2015-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5175 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14682971 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11095013 [patent_doc_number] => 20160291981 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-06 [patent_title] => 'REMOVING INVALID LITERAL LOAD VALUES, AND RELATED CIRCUITS, METHODS, AND COMPUTER-READABLE MEDIA' [patent_app_type] => utility [patent_app_number] => 14/679408 [patent_app_country] => US [patent_app_date] => 2015-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8370 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14679408 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11095159 [patent_doc_number] => 20160292127 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-06 [patent_title] => 'Low Energy Accelerator Processor Architecture with Short Parallel Instruction Word' [patent_app_type] => utility [patent_app_number] => 14/678939 [patent_app_country] => US [patent_app_date] => 2015-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 9961 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14678939 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13467153 [patent_doc_number] => 20180285119 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-04 [patent_title] => APPARATUS AND METHOD FOR INTER-STRAND COMMUNICATION [patent_app_type] => utility [patent_app_number] => 15/562408 [patent_app_country] => US [patent_app_date] => 2015-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22316 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15562408 [rel_patent_id] =>[rel_patent_doc_number] =>)