Michael J. Metzger

Array ( [id] => 10446677 [patent_doc_number] => 20150331691 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-19 [patent_title] => 'BRANCH PREDICTION USING MULTIPLE VERSIONS OF HISTORY DATA' [patent_app_type] => utility [patent_app_number] => 14/278000 [patent_app_country] => US [patent_app_date] => 2014-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4198 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14278000 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10439184 [patent_doc_number] => 20150324196 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-12 [patent_title] => 'UTILIZING PIPELINE REGISTERS AS INTERMEDIATE STORAGE' [patent_app_type] => utility [patent_app_number] => 14/275047 [patent_app_country] => US [patent_app_date] => 2014-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 13524 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14275047 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10962721 [patent_doc_number] => 20140365751 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-11 [patent_title] => 'OPERAND GENERATION IN AT LEAST ONE PROCESSING PIPELINE' [patent_app_type] => utility [patent_app_number] => 14/273723 [patent_app_country] => US [patent_app_date] => 2014-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6704 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14273723 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11786557 [patent_doc_number] => 09395991 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-07-19 [patent_title] => 'Speculative load issue' [patent_app_type] => utility [patent_app_number] => 14/169601 [patent_app_country] => US [patent_app_date] => 2014-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10905 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14169601 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14091309 [patent_doc_number] => 10241557 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-26 [patent_title] => Reducing power consumption in a processor [patent_app_type] => utility [patent_app_number] => 14/104042 [patent_app_country] => US [patent_app_date] => 2013-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7015 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14104042 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10275948 [patent_doc_number] => 20150160945 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-11 [patent_title] => 'ALLOCATION OF LOAD INSTRUCTION(S) TO A QUEUE BUFFER IN A PROCESSOR SYSTEM BASED ON PREDICTION OF AN INSTRUCTION PIPELINE HAZARD' [patent_app_type] => utility [patent_app_number] => 14/100228 [patent_app_country] => US [patent_app_date] => 2013-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10300 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14100228 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10269030 [patent_doc_number] => 20150154027 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-04 [patent_title] => 'THREAD OFFSET COUNTER' [patent_app_type] => utility [patent_app_number] => 14/096580 [patent_app_country] => US [patent_app_date] => 2013-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 7064 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14096580 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11791032 [patent_doc_number] => 09400657 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-07-26 [patent_title] => 'Dynamic management of a transaction retry indication' [patent_app_type] => utility [patent_app_number] => 13/868392 [patent_app_country] => US [patent_app_date] => 2013-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 29 [patent_no_of_words] => 30036 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13868392 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9200660 [patent_doc_number] => 20130339975 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-19 [patent_title] => 'MANAGEMENT OF SHARED TRANSACTIONAL RESOURCES' [patent_app_type] => utility [patent_app_number] => 13/868403 [patent_app_country] => US [patent_app_date] => 2013-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 30180 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13868403 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9745686 [patent_doc_number] => 20140281405 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'OPTIMIZING PERFORMANCE FOR CONTEXT-DEPENDENT INSTRUCTIONS' [patent_app_type] => utility [patent_app_number] => 13/841576 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5599 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13841576 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9200352 [patent_doc_number] => 20130339667 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-19 [patent_title] => 'SPECIAL CASE REGISTER UPDATE WITHOUT EXECUTION' [patent_app_type] => utility [patent_app_number] => 13/799670 [patent_app_country] => US [patent_app_date] => 2013-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5537 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13799670 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11220461 [patent_doc_number] => 09448797 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-20 [patent_title] => 'Restricted instructions in transactional execution' [patent_app_type] => utility [patent_app_number] => 13/783572 [patent_app_country] => US [patent_app_date] => 2013-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 29 [patent_no_of_words] => 30524 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13783572 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9200390 [patent_doc_number] => 20130339705 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-19 [patent_title] => 'RANDOMIZED TESTING WITHIN TRANSACTIONAL EXECUTION' [patent_app_type] => utility [patent_app_number] => 13/783357 [patent_app_country] => US [patent_app_date] => 2013-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 30395 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13783357 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9200389 [patent_doc_number] => 20130339704 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-19 [patent_title] => 'SAVING/RESTORING SELECTED REGISTERS IN TRANSACTIONAL PROCESSING' [patent_app_type] => utility [patent_app_number] => 13/783353 [patent_app_country] => US [patent_app_date] => 2013-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 28971 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13783353 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9200388 [patent_doc_number] => 20130339703 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-19 [patent_title] => 'RESTRICTING PROCESSING WITHIN A PROCESSOR TO FACILITATE TRANSACTION COMPLETION' [patent_app_type] => utility [patent_app_number] => 13/783312 [patent_app_country] => US [patent_app_date] => 2013-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 32915 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13783312 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11563665 [patent_doc_number] => 09626256 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-18 [patent_title] => 'Determining failure context in hardware transactional memories' [patent_app_type] => utility [patent_app_number] => 13/781658 [patent_app_country] => US [patent_app_date] => 2013-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3152 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13781658 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11577520 [patent_doc_number] => 09632781 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-25 [patent_title] => 'Vector register addressing and functions based on a scalar register data value' [patent_app_type] => utility [patent_app_number] => 13/777297 [patent_app_country] => US [patent_app_date] => 2013-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7605 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13777297 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9548980 [patent_doc_number] => 20140173627 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-19 [patent_title] => 'REQUESTING SHARED VARIABLE DIRECTORY (SVD) INFORMATION FROM A PLURALITY OF THREADS IN A PARALLEL COMPUTER' [patent_app_type] => utility [patent_app_number] => 13/766319 [patent_app_country] => US [patent_app_date] => 2013-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 13715 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13766319 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8855447 [patent_doc_number] => 20130145122 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-06 [patent_title] => 'INSTRUCTION PROCESSING METHOD OF NETWORK PROCESSOR AND NETWORK PROCESSOR' [patent_app_type] => utility [patent_app_number] => 13/763811 [patent_app_country] => US [patent_app_date] => 2013-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5552 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13763811 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11416598 [patent_doc_number] => 09563424 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-07 [patent_title] => 'Native code instruction selection' [patent_app_type] => utility [patent_app_number] => 13/756371 [patent_app_country] => US [patent_app_date] => 2013-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6180 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 306 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13756371 [rel_patent_id] =>[rel_patent_doc_number] =>)