Search

Michael J. Metzger

Examiner (ID: 19567, Phone: (571)272-3105 , Office: P/2182 )

Most Active Art Unit
2182
Art Unit(s)
2182, 2183
Total Applications
577
Issued Applications
477
Pending Applications
65
Abandoned Applications
48

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11584729 [patent_doc_number] => 09639371 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-02 [patent_title] => 'Solution to divergent branches in a SIMD core using hardware pointers' [patent_app_type] => utility [patent_app_number] => 13/753113 [patent_app_country] => US [patent_app_date] => 2013-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8276 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13753113 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/753113
Solution to divergent branches in a SIMD core using hardware pointers Jan 28, 2013 Issued
Array ( [id] => 9637076 [patent_doc_number] => 20140215185 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-31 [patent_title] => 'FETCHING INSTRUCTIONS OF A LOOP ROUTINE' [patent_app_type] => utility [patent_app_number] => 13/753380 [patent_app_country] => US [patent_app_date] => 2013-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3656 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13753380 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/753380
FETCHING INSTRUCTIONS OF A LOOP ROUTINE Jan 28, 2013 Abandoned
Array ( [id] => 12932872 [patent_doc_number] => 09830164 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-11-28 [patent_title] => Hardware and software solutions to divergent branches in a parallel pipeline [patent_app_type] => utility [patent_app_number] => 13/753098 [patent_app_country] => US [patent_app_date] => 2013-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7697 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13753098 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/753098
Hardware and software solutions to divergent branches in a parallel pipeline Jan 28, 2013 Issued
Array ( [id] => 8831663 [patent_doc_number] => 20130132708 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-23 [patent_title] => 'MULTI-CORE PROCESSOR SYSTEM, COMPUTER PRODUCT, AND CONTROL METHOD' [patent_app_type] => utility [patent_app_number] => 13/748132 [patent_app_country] => US [patent_app_date] => 2013-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6755 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13748132 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/748132
MULTI-CORE PROCESSOR SYSTEM, COMPUTER PRODUCT, AND CONTROL METHOD Jan 22, 2013 Abandoned
Array ( [id] => 10976991 [patent_doc_number] => 20140380025 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-25 [patent_title] => 'MANAGEMENT OF HARDWARE ACCELERATOR CONFIGURATIONS IN A PROCESSOR CHIP' [patent_app_type] => utility [patent_app_number] => 14/123231 [patent_app_country] => US [patent_app_date] => 2013-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9509 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14123231 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/123231
MANAGEMENT OF HARDWARE ACCELERATOR CONFIGURATIONS IN A PROCESSOR CHIP Jan 22, 2013 Abandoned
Array ( [id] => 11306512 [patent_doc_number] => 09513910 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-12-06 [patent_title] => 'Requesting shared variable directory (SVD) information from a plurality of threads in a parallel computer' [patent_app_type] => utility [patent_app_number] => 13/718259 [patent_app_country] => US [patent_app_date] => 2012-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 13683 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 306 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13718259 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/718259
Requesting shared variable directory (SVD) information from a plurality of threads in a parallel computer Dec 17, 2012 Issued
Array ( [id] => 11860815 [patent_doc_number] => 09740498 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-22 [patent_title] => 'Opportunistic multi-thread method and processor' [patent_app_type] => utility [patent_app_number] => 14/357871 [patent_app_country] => US [patent_app_date] => 2012-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1836 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14357871 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/357871
Opportunistic multi-thread method and processor Nov 14, 2012 Issued
Array ( [id] => 10934585 [patent_doc_number] => 20140337606 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-13 [patent_title] => 'DIGITAL SIGNAL PROCESSOR, PROGRAM CONTROL METHOD, AND CONTROL PROGRAM' [patent_app_type] => utility [patent_app_number] => 14/356816 [patent_app_country] => US [patent_app_date] => 2012-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9602 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14356816 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/356816
Digital signal processor, program control method, and control program Nov 1, 2012 Issued
Array ( [id] => 9451635 [patent_doc_number] => 20140122805 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-01 [patent_title] => 'SELECTIVE POISONING OF DATA DURING RUNAHEAD' [patent_app_type] => utility [patent_app_number] => 13/662171 [patent_app_country] => US [patent_app_date] => 2012-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6905 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13662171 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/662171
Selective poisoning of data during runahead Oct 25, 2012 Issued
Array ( [id] => 11577526 [patent_doc_number] => 09632787 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-25 [patent_title] => 'Data processing system with data characteristic based identification of corresponding instructions' [patent_app_type] => utility [patent_app_number] => 13/658372 [patent_app_country] => US [patent_app_date] => 2012-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4835 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13658372 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/658372
Data processing system with data characteristic based identification of corresponding instructions Oct 22, 2012 Issued
Array ( [id] => 8893696 [patent_doc_number] => 20130166880 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-27 [patent_title] => 'PROCESSING DEVICE AND METHOD FOR CONTROLLING PROCESSING DEVICE' [patent_app_type] => utility [patent_app_number] => 13/656994 [patent_app_country] => US [patent_app_date] => 2012-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7991 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13656994 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/656994
PROCESSING DEVICE AND METHOD FOR CONTROLLING PROCESSING DEVICE Oct 21, 2012 Abandoned
Array ( [id] => 13068895 [patent_doc_number] => 10055227 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-21 [patent_title] => Using the least significant bits of a called function's address to switch processor modes [patent_app_type] => utility [patent_app_number] => 13/655499 [patent_app_country] => US [patent_app_date] => 2012-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5762 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13655499 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/655499
Using the least significant bits of a called function's address to switch processor modes Oct 18, 2012 Issued
Array ( [id] => 9437397 [patent_doc_number] => 20140115304 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-24 [patent_title] => 'COMPRESSED INSTRUCTION CODE STORAGE' [patent_app_type] => utility [patent_app_number] => 13/654482 [patent_app_country] => US [patent_app_date] => 2012-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6783 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13654482 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/654482
COMPRESSED INSTRUCTION CODE STORAGE Oct 17, 2012 Abandoned
Array ( [id] => 11550435 [patent_doc_number] => 09619284 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-11 [patent_title] => 'Dynamically switching a workload between heterogeneous cores of a processor' [patent_app_type] => utility [patent_app_number] => 13/645081 [patent_app_country] => US [patent_app_date] => 2012-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8397 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13645081 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/645081
Dynamically switching a workload between heterogeneous cores of a processor Oct 3, 2012 Issued
Array ( [id] => 12255925 [patent_doc_number] => 09928067 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-27 [patent_title] => 'Methods and systems for performing a binary translation' [patent_app_type] => utility [patent_app_number] => 13/976359 [patent_app_country] => US [patent_app_date] => 2012-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 11849 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13976359 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/976359
Methods and systems for performing a binary translation Sep 20, 2012 Issued
Array ( [id] => 11550497 [patent_doc_number] => 09619345 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-11 [patent_title] => 'Apparatus for determining failure context in hardware transactional memories' [patent_app_type] => utility [patent_app_number] => 13/615241 [patent_app_country] => US [patent_app_date] => 2012-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3246 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13615241 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/615241
Apparatus for determining failure context in hardware transactional memories Sep 12, 2012 Issued
Array ( [id] => 11452112 [patent_doc_number] => 09575756 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-21 [patent_title] => 'Predication in a vector processor' [patent_app_type] => utility [patent_app_number] => 13/569349 [patent_app_country] => US [patent_app_date] => 2012-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7263 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 306 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13569349 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/569349
Predication in a vector processor Aug 7, 2012 Issued
Array ( [id] => 11430895 [patent_doc_number] => 09569211 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-14 [patent_title] => 'Predication in a vector processor' [patent_app_type] => utility [patent_app_number] => 13/566129 [patent_app_country] => US [patent_app_date] => 2012-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7197 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 273 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13566129 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/566129
Predication in a vector processor Aug 2, 2012 Issued
Array ( [id] => 8466875 [patent_doc_number] => 20120272043 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-25 [patent_title] => 'REQUEST COALESCING FOR INSTRUCTION STREAMS' [patent_app_type] => utility [patent_app_number] => 13/538765 [patent_app_country] => US [patent_app_date] => 2012-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10130 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13538765 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/538765
Request coalescing for instruction streams Jun 28, 2012 Issued
Array ( [id] => 11220460 [patent_doc_number] => 09448796 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-20 [patent_title] => 'Restricted instructions in transactional execution' [patent_app_type] => utility [patent_app_number] => 13/524765 [patent_app_country] => US [patent_app_date] => 2012-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 29 [patent_no_of_words] => 30508 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13524765 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/524765
Restricted instructions in transactional execution Jun 14, 2012 Issued
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