Search

Michael J. Metzger

Examiner (ID: 19567, Phone: (571)272-3105 , Office: P/2182 )

Most Active Art Unit
2182
Art Unit(s)
2182, 2183
Total Applications
577
Issued Applications
477
Pending Applications
65
Abandoned Applications
48

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9137203 [patent_doc_number] => 20130297918 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-07 [patent_title] => 'Apparatus for Predicate Calculation in Processor Instruction Set' [patent_app_type] => utility [patent_app_number] => 13/461950 [patent_app_country] => US [patent_app_date] => 2012-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5995 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13461950 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/461950
Apparatus for predicate calculation in processor instruction set May 1, 2012 Issued
Array ( [id] => 8485080 [patent_doc_number] => 20120284487 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-08 [patent_title] => 'Vector Slot Processor Execution Unit for High Speed Streaming Inputs' [patent_app_type] => utility [patent_app_number] => 13/462144 [patent_app_country] => US [patent_app_date] => 2012-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 8120 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13462144 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/462144
Vector slot processor execution unit for high speed streaming inputs May 1, 2012 Issued
Array ( [id] => 9123758 [patent_doc_number] => 20130290680 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-31 [patent_title] => 'OPTIMIZING REGISTER INITIALIZATION OPERATIONS' [patent_app_type] => utility [patent_app_number] => 13/460268 [patent_app_country] => US [patent_app_date] => 2012-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8953 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13460268 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/460268
Optimizing register initialization operations Apr 29, 2012 Issued
Array ( [id] => 9599101 [patent_doc_number] => 20140195782 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-10 [patent_title] => 'METHOD AND APPARATUS TO PROCESS SHA-2 SECURE HASHING ALGORITHM' [patent_app_type] => utility [patent_app_number] => 13/976274 [patent_app_country] => US [patent_app_date] => 2012-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 21200 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13976274 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/976274
Method and apparatus to process SHA-2 secure hashing algorithm Mar 29, 2012 Issued
Array ( [id] => 9200346 [patent_doc_number] => 20130339661 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-19 [patent_title] => 'EFFICIENT ZERO-BASED DECOMPRESSION' [patent_app_type] => utility [patent_app_number] => 13/991858 [patent_app_country] => US [patent_app_date] => 2011-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 16782 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13991858 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/991858
Efficient zero-based decompression Dec 29, 2011 Issued
Array ( [id] => 9840919 [patent_doc_number] => 20150033001 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-29 [patent_title] => 'METHOD, DEVICE AND SYSTEM FOR CONTROL SIGNALLING IN A DATA PATH MODULE OF A DATA STREAM PROCESSING ENGINE' [patent_app_type] => utility [patent_app_number] => 13/994582 [patent_app_country] => US [patent_app_date] => 2011-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 14750 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13994582 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/994582
Method, device and system for control signaling in a data path module of a data stream processing engine Dec 28, 2011 Issued
Array ( [id] => 9658710 [patent_doc_number] => 20140229715 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-14 [patent_title] => 'APPARATUS AND METHOD FOR PROVIDING EVENTING IP AND SOURCE DATA ADDRESS IN A STATISTICAL SAMPLING INFRASTRUCTURE' [patent_app_type] => utility [patent_app_number] => 13/976613 [patent_app_country] => US [patent_app_date] => 2011-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4000 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13976613 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/976613
APPARATUS AND METHOD FOR PROVIDING EVENTING IP AND SOURCE DATA ADDRESS IN A STATISTICAL SAMPLING INFRASTRUCTURE Dec 28, 2011 Abandoned
Array ( [id] => 11232637 [patent_doc_number] => 09459865 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-10-04 [patent_title] => 'Systems, apparatuses, and methods for performing a butterfly horizontal and cross add or substract in response to a single instruction' [patent_app_type] => utility [patent_app_number] => 13/992236 [patent_app_country] => US [patent_app_date] => 2011-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 25 [patent_no_of_words] => 17214 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 355 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13992236 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/992236
Systems, apparatuses, and methods for performing a butterfly horizontal and cross add or substract in response to a single instruction Dec 22, 2011 Issued
Array ( [id] => 9123750 [patent_doc_number] => 20130290672 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-31 [patent_title] => 'APPARATUS AND METHOD OF MASK PERMUTE INSTRUCTIONS' [patent_app_type] => utility [patent_app_number] => 13/976435 [patent_app_country] => US [patent_app_date] => 2011-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 16397 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13976435 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/976435
Apparatus and method of mask permute instructions Dec 22, 2011 Issued
Array ( [id] => 12011534 [patent_doc_number] => 09804852 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-31 [patent_title] => 'Conditional execution support for ISA instructions using prefixes' [patent_app_type] => utility [patent_app_number] => 13/976230 [patent_app_country] => US [patent_app_date] => 2011-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5947 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13976230 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/976230
Conditional execution support for ISA instructions using prefixes Nov 29, 2011 Issued
Array ( [id] => 10922164 [patent_doc_number] => 20140325183 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-30 [patent_title] => 'INTEGRATED CIRCUIT DEVICE, ASYMMETRIC MULTI-CORE PROCESSING MODULE, ELECTRONIC DEVICE AND METHOD OF MANAGING EXECUTION OF COMPUTER PROGRAM CODE THEREFOR' [patent_app_type] => utility [patent_app_number] => 14/358053 [patent_app_country] => US [patent_app_date] => 2011-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5639 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14358053 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/358053
INTEGRATED CIRCUIT DEVICE, ASYMMETRIC MULTI-CORE PROCESSING MODULE, ELECTRONIC DEVICE AND METHOD OF MANAGING EXECUTION OF COMPUTER PROGRAM CODE THEREFOR Nov 27, 2011 Abandoned
Array ( [id] => 9137200 [patent_doc_number] => 20130297915 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-07 [patent_title] => 'FLAG NON-MODIFICATION EXTENSION FOR ISA INSTRUCTIONS USING PREFIXES' [patent_app_type] => utility [patent_app_number] => 13/976261 [patent_app_country] => US [patent_app_date] => 2011-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5056 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13976261 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/976261
Flag non-modification extension for ISA instructions using prefixes Nov 3, 2011 Issued
Array ( [id] => 9071070 [patent_doc_number] => 20130262826 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-03 [patent_title] => 'APPARATUS AND METHOD FOR DYNAMICALLY MANAGING MEMORY ACCESS BANDWIDTH IN MULTI-CORE PROCESSOR' [patent_app_type] => utility [patent_app_number] => 13/991619 [patent_app_country] => US [patent_app_date] => 2011-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3423 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13991619 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/991619
APPARATUS AND METHOD FOR DYNAMICALLY MANAGING MEMORY ACCESS BANDWIDTH IN MULTI-CORE PROCESSOR Oct 5, 2011 Abandoned
Array ( [id] => 9548599 [patent_doc_number] => 20140173247 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-19 [patent_title] => 'PROCESSING APPARATUS AND METHOD OF SYNCHRONIZING A FIRST PROCESSING UNIT AND A SECOND PROCESSING UNIT' [patent_app_type] => utility [patent_app_number] => 14/125200 [patent_app_country] => US [patent_app_date] => 2011-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6958 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14125200 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/125200
Processing apparatus and method of synchronizing a first processing unit and a second processing unit Jul 19, 2011 Issued
Array ( [id] => 10562390 [patent_doc_number] => 09286066 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-15 [patent_title] => 'Processor, and method of loop count control by processor' [patent_app_type] => utility [patent_app_number] => 13/508977 [patent_app_country] => US [patent_app_date] => 2010-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4370 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13508977 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/508977
Processor, and method of loop count control by processor Oct 14, 2010 Issued
Array ( [id] => 11584809 [patent_doc_number] => 09639451 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-02 [patent_title] => 'Debugger system, method and computer program product for utilizing hardware breakpoints for debugging instructions' [patent_app_type] => utility [patent_app_number] => 13/522382 [patent_app_country] => US [patent_app_date] => 2010-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3504 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13522382 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/522382
Debugger system, method and computer program product for utilizing hardware breakpoints for debugging instructions Jan 24, 2010 Issued
Array ( [id] => 7679654 [patent_doc_number] => 20100106933 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-29 [patent_title] => 'METHOD AND SYSTEM FOR MANAGING STORAGE CAPACITY IN A STORAGE NETWORK' [patent_app_type] => utility [patent_app_number] => 12/259145 [patent_app_country] => US [patent_app_date] => 2008-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5201 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0106/20100106933.pdf [firstpage_image] =>[orig_patent_app_number] => 12259145 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/259145
Method and system for managing storage capacity in a storage network Oct 26, 2008 Issued
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