Search

Michael J. Metzger

Examiner (ID: 19567, Phone: (571)272-3105 , Office: P/2182 )

Most Active Art Unit
2182
Art Unit(s)
2182, 2183
Total Applications
577
Issued Applications
477
Pending Applications
65
Abandoned Applications
48

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20563998 [patent_doc_number] => 12566607 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-03 [patent_title] => Robust, efficient multiprocessor-coprocessor interface [patent_app_type] => utility [patent_app_number] => 18/596106 [patent_app_country] => US [patent_app_date] => 2024-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 42 [patent_no_of_words] => 32587 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18596106 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/596106
Robust, efficient multiprocessor-coprocessor interface Mar 4, 2024 Issued
Array ( [id] => 20415795 [patent_doc_number] => 12499081 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-16 [patent_title] => Vector reduction processor [patent_app_type] => utility [patent_app_number] => 18/429142 [patent_app_country] => US [patent_app_date] => 2024-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9865 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18429142 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/429142
Vector reduction processor Jan 30, 2024 Issued
Array ( [id] => 19160051 [patent_doc_number] => 20240152758 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-09 [patent_title] => NEURAL NETWORK ACTIVATION COMPRESSION WITH NON-UNIFORM MANTISSAS [patent_app_type] => utility [patent_app_number] => 18/415159 [patent_app_country] => US [patent_app_date] => 2024-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21135 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18415159 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/415159
Neural network activation compression with non-uniform mantissas Jan 16, 2024 Issued
Array ( [id] => 19747842 [patent_doc_number] => 20250036407 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-30 [patent_title] => INTER-PROCESS SERVING OF MACHINE LEARNING FEATURES FROM MAPPED MEMORY FOR MACHINE LEARNING MODELS [patent_app_type] => utility [patent_app_number] => 18/413776 [patent_app_country] => US [patent_app_date] => 2024-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4926 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18413776 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/413776
Inter-process serving of machine learning features from mapped memory for machine learning models Jan 15, 2024 Issued
Array ( [id] => 20550346 [patent_doc_number] => 12561139 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-24 [patent_title] => Encoding and decoding variable length instructions [patent_app_type] => utility [patent_app_number] => 18/406527 [patent_app_country] => US [patent_app_date] => 2024-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 11917 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18406527 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/406527
Encoding and decoding variable length instructions Jan 7, 2024 Issued
Array ( [id] => 19144544 [patent_doc_number] => 20240143457 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => HIGH PERFORMANCE PROCESSOR FOR LOW-WAY AND HIGH-LATENCY MEMORY INSTANCES [patent_app_type] => utility [patent_app_number] => 18/406346 [patent_app_country] => US [patent_app_date] => 2024-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 36283 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18406346 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/406346
High performance processor for low-way and high-latency memory instances Jan 7, 2024 Issued
Array ( [id] => 19979215 [patent_doc_number] => 12346692 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-01 [patent_title] => Computer processor for higher precision computations using a mixed-precision decomposition of operations [patent_app_type] => utility [patent_app_number] => 18/402606 [patent_app_country] => US [patent_app_date] => 2024-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 38 [patent_no_of_words] => 21044 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18402606 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/402606
Computer processor for higher precision computations using a mixed-precision decomposition of operations Jan 1, 2024 Issued
Array ( [id] => 19934045 [patent_doc_number] => 12307250 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-20 [patent_title] => Systems and methods for performing 16-bit floating-point matrix dot product instructions [patent_app_type] => utility [patent_app_number] => 18/397664 [patent_app_country] => US [patent_app_date] => 2023-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 47 [patent_no_of_words] => 19684 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 325 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18397664 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/397664
Systems and methods for performing 16-bit floating-point matrix dot product instructions Dec 26, 2023 Issued
Array ( [id] => 19084735 [patent_doc_number] => 20240111536 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-04 [patent_title] => DATA PROCESSING APPARATUS AND RELATED PRODUCTS [patent_app_type] => utility [patent_app_number] => 18/531734 [patent_app_country] => US [patent_app_date] => 2023-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 77457 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18531734 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/531734
Data processing apparatus and related products Dec 6, 2023 Issued
Array ( [id] => 20403492 [patent_doc_number] => 12493465 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-09 [patent_title] => Vector load store operations in a vector pipeline using a single operation in a load store unit [patent_app_type] => utility [patent_app_number] => 18/524222 [patent_app_country] => US [patent_app_date] => 2023-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4894 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18524222 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/524222
Vector load store operations in a vector pipeline using a single operation in a load store unit Nov 29, 2023 Issued
Array ( [id] => 20034923 [patent_doc_number] => 20250173145 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-29 [patent_title] => FILTERING BRANCH INSTRUCTION PREDICTIONS [patent_app_type] => utility [patent_app_number] => 18/520983 [patent_app_country] => US [patent_app_date] => 2023-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4881 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18520983 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/520983
FILTERING BRANCH INSTRUCTION PREDICTIONS Nov 27, 2023 Pending
Array ( [id] => 20782119 [patent_doc_number] => 20260170316 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-06-18 [patent_title] => THREAD TILING FOR MEMORY LATENCY REDUCTION [patent_app_type] => utility [patent_app_number] => 18/567544 [patent_app_country] => US [patent_app_date] => 2023-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18567544 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/567544
THREAD TILING FOR MEMORY LATENCY REDUCTION Nov 26, 2023 Pending
Array ( [id] => 20017965 [patent_doc_number] => 20250156187 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-15 [patent_title] => REDUCTION OF DATA TRANSFER OVERHEAD [patent_app_type] => utility [patent_app_number] => 18/510088 [patent_app_country] => US [patent_app_date] => 2023-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3496 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18510088 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/510088
Reduction of data transfer overhead Nov 14, 2023 Issued
Array ( [id] => 19617370 [patent_doc_number] => 20240403050 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => VECTOR COMPARISON AND/OR POPULATION COUNT OPERATIONS [patent_app_type] => utility [patent_app_number] => 18/509121 [patent_app_country] => US [patent_app_date] => 2023-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14669 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18509121 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/509121
VECTOR COMPARISON AND/OR POPULATION COUNT OPERATIONS Nov 13, 2023 Pending
Array ( [id] => 20110052 [patent_doc_number] => 12360773 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-15 [patent_title] => Thread commencement using a work descriptor packet in a self-scheduling processor [patent_app_type] => utility [patent_app_number] => 18/387045 [patent_app_country] => US [patent_app_date] => 2023-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 20020 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 305 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18387045 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/387045
Thread commencement using a work descriptor packet in a self-scheduling processor Nov 4, 2023 Issued
Array ( [id] => 19625635 [patent_doc_number] => 12164464 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-10 [patent_title] => Multi-threaded, self-scheduling processor [patent_app_type] => utility [patent_app_number] => 18/386880 [patent_app_country] => US [patent_app_date] => 2023-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 25246 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 289 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18386880 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/386880
Multi-threaded, self-scheduling processor Nov 2, 2023 Issued
Array ( [id] => 18974006 [patent_doc_number] => 20240054098 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-15 [patent_title] => FETCHING VECTOR DATA ELEMENTS WITH PADDING [patent_app_type] => utility [patent_app_number] => 18/496013 [patent_app_country] => US [patent_app_date] => 2023-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21328 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18496013 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/496013
Fetching vector data elements with padding Oct 26, 2023 Issued
Array ( [id] => 20773456 [patent_doc_number] => 12657130 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-16 [patent_title] => Neural processing device and load/store method of neural processing device [patent_app_type] => utility [patent_app_number] => 18/494696 [patent_app_country] => US [patent_app_date] => 2023-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 15184 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18494696 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/494696
Neural processing device and load/store method of neural processing device Oct 24, 2023 Issued
Array ( [id] => 18957348 [patent_doc_number] => 20240045675 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-08 [patent_title] => Apparatus for Calculating and Retaining a Bound on Error during Floating-Point Operations and Methods Thereof [patent_app_type] => utility [patent_app_number] => 18/492214 [patent_app_country] => US [patent_app_date] => 2023-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17725 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18492214 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/492214
Apparatus for Calculating and Retaining a Bound on Error during Floating-Point Operations and Methods Thereof Oct 22, 2023 Abandoned
Array ( [id] => 19878487 [patent_doc_number] => 20250110744 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-03 [patent_title] => BTB PREFECTHING VIA BACK-ANNOTATION [patent_app_type] => utility [patent_app_number] => 18/374363 [patent_app_country] => US [patent_app_date] => 2023-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9697 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18374363 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/374363
BTB prefetching via back-annotation Sep 27, 2023 Issued
Menu