
Michael J. Metzger
Examiner (ID: 15061, Phone: (571)272-3105 , Office: P/2182 )
| Most Active Art Unit | 2182 |
| Art Unit(s) | 2182, 2183 |
| Total Applications | 559 |
| Issued Applications | 467 |
| Pending Applications | 60 |
| Abandoned Applications | 48 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 19383079
[patent_doc_number] => 20240272949
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-15
[patent_title] => NEURAL NETWORK ACCELERATOR ARCHITECTURE BASED ON CUSTOM INSTRUCTION AND DMA ON FPGA
[patent_app_type] => utility
[patent_app_number] => 18/169003
[patent_app_country] => US
[patent_app_date] => 2023-02-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2994
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18169003
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/169003 | Neural network accelerator architecture based on custom instruction and DMA on FPGA | Feb 13, 2023 | Issued |
Array
(
[id] => 18553827
[patent_doc_number] => 20230251839
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-08-10
[patent_title] => Head Of Line Blocking Mitigation In A Reconfigurable Data Processor
[patent_app_type] => utility
[patent_app_number] => 18/107613
[patent_app_country] => US
[patent_app_date] => 2023-02-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 15335
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18107613
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/107613 | Head of line blocking mitigation in a reconfigurable data processor | Feb 8, 2023 | Issued |
Array
(
[id] => 18539793
[patent_doc_number] => 20230244901
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-08-03
[patent_title] => COMPUTE-IN-MEMORY SRAM USING MEMORY-IMMERSED DATA CONVERSION AND MULTIPLICATION-FREE OPERATORS
[patent_app_type] => utility
[patent_app_number] => 18/161830
[patent_app_country] => US
[patent_app_date] => 2023-01-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7384
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 45
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18161830
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/161830 | COMPUTE-IN-MEMORY SRAM USING MEMORY-IMMERSED DATA CONVERSION AND MULTIPLICATION-FREE OPERATORS | Jan 29, 2023 | Pending |
Array
(
[id] => 20027032
[patent_doc_number] => 20250165254
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-05-22
[patent_title] => LOOPING INSTRUCTION
[patent_app_type] => utility
[patent_app_number] => 18/841082
[patent_app_country] => US
[patent_app_date] => 2023-01-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5109
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18841082
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/841082 | LOOPING INSTRUCTION | Jan 24, 2023 | Issued |
Array
(
[id] => 18513393
[patent_doc_number] => 20230229623
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-07-20
[patent_title] => Fracturable Data Path in a Reconfigurable Data Processor
[patent_app_type] => utility
[patent_app_number] => 18/099218
[patent_app_country] => US
[patent_app_date] => 2023-01-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 34415
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 184
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18099218
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/099218 | Fracturable data path in a reconfigurable data processor | Jan 18, 2023 | Issued |
Array
(
[id] => 18378026
[patent_doc_number] => 20230153113
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-05-18
[patent_title] => System and Method for Instruction Unwinding in an Out-of-Order Processor
[patent_app_type] => utility
[patent_app_number] => 18/156042
[patent_app_country] => US
[patent_app_date] => 2023-01-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 23268
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -42
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18156042
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/156042 | System and method for instruction unwinding in an out-of-order processor | Jan 17, 2023 | Issued |
Array
(
[id] => 18378025
[patent_doc_number] => 20230153112
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-05-18
[patent_title] => COMPUTER SYSTEM AND METHOD FOR VALIDATION OF PARALLELIZED COMPUTER PROGRAMS
[patent_app_type] => utility
[patent_app_number] => 18/156237
[patent_app_country] => US
[patent_app_date] => 2023-01-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14626
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 213
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18156237
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/156237 | Computer system and method for validation of parallelized computer programs | Jan 17, 2023 | Issued |
Array
(
[id] => 18378062
[patent_doc_number] => 20230153149
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-05-18
[patent_title] => DYNAMIC GRAPHICAL PROCESSING UNIT REGISTER ALLOCATION
[patent_app_type] => utility
[patent_app_number] => 18/154012
[patent_app_country] => US
[patent_app_date] => 2023-01-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9705
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => 0
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18154012
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/154012 | DYNAMIC GRAPHICAL PROCESSING UNIT REGISTER ALLOCATION | Jan 11, 2023 | Pending |
Array
(
[id] => 18393402
[patent_doc_number] => 20230161622
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-05-25
[patent_title] => System and Method for Low Latency Node Local Scheduling in Distributed Resource Management
[patent_app_type] => utility
[patent_app_number] => 18/151946
[patent_app_country] => US
[patent_app_date] => 2023-01-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8925
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18151946
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/151946 | System and method for low latency node local scheduling in distributed resource management | Jan 8, 2023 | Issued |
Array
(
[id] => 19653457
[patent_doc_number] => 12175249
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-12-24
[patent_title] => System, device and/or method for processing signal streams
[patent_app_type] => utility
[patent_app_number] => 18/149758
[patent_app_country] => US
[patent_app_date] => 2023-01-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 17881
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18149758
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/149758 | System, device and/or method for processing signal streams | Jan 3, 2023 | Issued |
Array
(
[id] => 18352074
[patent_doc_number] => 20230140185
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-05-04
[patent_title] => NEURAL NETWORK ACTIVATION COMPRESSION WITH NON-UNIFORM MANTISSAS
[patent_app_type] => utility
[patent_app_number] => 18/092876
[patent_app_country] => US
[patent_app_date] => 2023-01-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 22037
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18092876
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/092876 | Neural network activation compression with non-uniform mantissas | Jan 2, 2023 | Issued |
Array
(
[id] => 19283970
[patent_doc_number] => 20240220446
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-07-04
[patent_title] => METHODS, SYSTEMS, AND APPARATUSES FOR DYNAMIC SIMULTANEOUS MULTI-THREADING (SMT) SCHEDULING TO MAXIMIZE PROCESSOR PERFORMANCE ON HYBRID PLATFORMS
[patent_app_type] => utility
[patent_app_number] => 18/149072
[patent_app_country] => US
[patent_app_date] => 2022-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 27772
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 206
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18149072
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/149072 | METHODS, SYSTEMS, AND APPARATUSES FOR DYNAMIC SIMULTANEOUS MULTI-THREADING (SMT) SCHEDULING TO MAXIMIZE PROCESSOR PERFORMANCE ON HYBRID PLATFORMS | Dec 29, 2022 | Pending |
Array
(
[id] => 18889997
[patent_doc_number] => 11868770
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-01-09
[patent_title] => Computer processor for higher precision computations using a mixed-precision decomposition of operations
[patent_app_type] => utility
[patent_app_number] => 18/091157
[patent_app_country] => US
[patent_app_date] => 2022-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 29
[patent_figures_cnt] => 38
[patent_no_of_words] => 25126
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 194
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18091157
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/091157 | Computer processor for higher precision computations using a mixed-precision decomposition of operations | Dec 28, 2022 | Issued |
Array
(
[id] => 19841957
[patent_doc_number] => 12254348
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-03-18
[patent_title] => Information processing apparatus, information processing method, and recording medium for performing inference processing using an inference model
[patent_app_type] => utility
[patent_app_number] => 18/090639
[patent_app_country] => US
[patent_app_date] => 2022-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 15
[patent_no_of_words] => 14087
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 223
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18090639
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/090639 | Information processing apparatus, information processing method, and recording medium for performing inference processing using an inference model | Dec 28, 2022 | Issued |
Array
(
[id] => 18974007
[patent_doc_number] => 20240054099
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-02-15
[patent_title] => Cluster-Based Placement and Routing of Memory Units and Compute Units in a Reconfigurable Computing Grid
[patent_app_type] => utility
[patent_app_number] => 18/083362
[patent_app_country] => US
[patent_app_date] => 2022-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11901
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 190
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18083362
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/083362 | Cluster-based placement and routing of memory units and compute units in a reconfigurable computing grid | Dec 15, 2022 | Issued |
Array
(
[id] => 18305852
[patent_doc_number] => 20230109752
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-04-13
[patent_title] => DETERMINISTIC REPLAY OF A MULTI-THREADED TRACE ON A MULTI-THREADED PROCESSOR
[patent_app_type] => utility
[patent_app_number] => 18/064225
[patent_app_country] => US
[patent_app_date] => 2022-12-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 36423
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -11
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18064225
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/064225 | Deterministic replay of a multi-threaded trace on a multi-threaded processor | Dec 8, 2022 | Issued |
Array
(
[id] => 19136886
[patent_doc_number] => 11971844
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-04-30
[patent_title] => Chiplet system and positioning method thereof
[patent_app_type] => utility
[patent_app_number] => 18/070514
[patent_app_country] => US
[patent_app_date] => 2022-11-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 12
[patent_no_of_words] => 2840
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18070514
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/070514 | Chiplet system and positioning method thereof | Nov 28, 2022 | Issued |
Array
(
[id] => 18270190
[patent_doc_number] => 20230091432
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-23
[patent_title] => Thread Creation on Local or Remote Compute Elements by a Multi-Threaded, Self-Scheduling Processor
[patent_app_type] => utility
[patent_app_number] => 17/994143
[patent_app_country] => US
[patent_app_date] => 2022-11-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 25239
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -20
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17994143
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/994143 | Thread creation on local or remote compute elements by a multi-threaded, self-scheduling processor | Nov 24, 2022 | Issued |
Array
(
[id] => 19189894
[patent_doc_number] => 20240168807
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-05-23
[patent_title] => CROSS-THREAD REGISTER SHARING FOR MATRIX MULTIPLICATION COMPUTE
[patent_app_type] => utility
[patent_app_number] => 18/056949
[patent_app_country] => US
[patent_app_date] => 2022-11-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 52625
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18056949
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/056949 | CROSS-THREAD REGISTER SHARING FOR MATRIX MULTIPLICATION COMPUTE | Nov 17, 2022 | Pending |
Array
(
[id] => 19443417
[patent_doc_number] => 12093688
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-09-17
[patent_title] => Multibit shift instruction
[patent_app_type] => utility
[patent_app_number] => 17/989067
[patent_app_country] => US
[patent_app_date] => 2022-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 10216
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 160
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17989067
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/989067 | Multibit shift instruction | Nov 16, 2022 | Issued |