Search

Michael J. Simitoski

Examiner (ID: 2333, Phone: (571)272-3841 , Office: P/2493 )

Most Active Art Unit
2493
Art Unit(s)
2134, 2493, 2434, 2439
Total Applications
1072
Issued Applications
810
Pending Applications
69
Abandoned Applications
206

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18766737 [patent_doc_number] => 11817144 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-14 [patent_title] => Arrangements of memory devices and methods of operating the memory devices [patent_app_type] => utility [patent_app_number] => 17/313179 [patent_app_country] => US [patent_app_date] => 2021-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7839 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17313179 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/313179
Arrangements of memory devices and methods of operating the memory devices May 5, 2021 Issued
Array ( [id] => 18120350 [patent_doc_number] => 11551748 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-10 [patent_title] => System and method for recycling energy of static random-access memory (SRAM) write circuit [patent_app_type] => utility [patent_app_number] => 17/307943 [patent_app_country] => US [patent_app_date] => 2021-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5191 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17307943 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/307943
System and method for recycling energy of static random-access memory (SRAM) write circuit May 3, 2021 Issued
Array ( [id] => 17963379 [patent_doc_number] => 20220343960 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-27 [patent_title] => REFERENCE GENERATION FOR NARROW-RANGE SENSE AMPLIFIERS [patent_app_type] => utility [patent_app_number] => 17/239505 [patent_app_country] => US [patent_app_date] => 2021-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9216 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17239505 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/239505
Reference generation for narrow-range sense amplifiers Apr 22, 2021 Issued
Array ( [id] => 17010664 [patent_doc_number] => 20210241825 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-05 [patent_title] => MEMORY DEVICE WITH SIGNAL EDGE SHARPENER CIRCUITRY [patent_app_type] => utility [patent_app_number] => 17/234160 [patent_app_country] => US [patent_app_date] => 2021-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8018 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17234160 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/234160
Memory device with signal edge sharpener circuitry Apr 18, 2021 Issued
Array ( [id] => 18967217 [patent_doc_number] => 11900995 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-13 [patent_title] => Wordline modulation techniques [patent_app_type] => utility [patent_app_number] => 17/223950 [patent_app_country] => US [patent_app_date] => 2021-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6399 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17223950 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/223950
Wordline modulation techniques Apr 5, 2021 Issued
Array ( [id] => 17173830 [patent_doc_number] => 20210327501 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-21 [patent_title] => LOWER POWER MEMORY WRITE OPERATION [patent_app_type] => utility [patent_app_number] => 17/221383 [patent_app_country] => US [patent_app_date] => 2021-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4489 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17221383 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/221383
LOWER POWER MEMORY WRITE OPERATION Apr 1, 2021 Abandoned
Array ( [id] => 18120349 [patent_doc_number] => 11551747 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-10 [patent_title] => Computation apparatus and method using the same [patent_app_type] => utility [patent_app_number] => 17/213182 [patent_app_country] => US [patent_app_date] => 2021-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5520 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17213182 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/213182
Computation apparatus and method using the same Mar 24, 2021 Issued
Array ( [id] => 18431430 [patent_doc_number] => 11676657 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-13 [patent_title] => Time-interleaving sensing scheme for pseudo dual-port memory [patent_app_type] => utility [patent_app_number] => 17/210521 [patent_app_country] => US [patent_app_date] => 2021-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3060 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17210521 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/210521
Time-interleaving sensing scheme for pseudo dual-port memory Mar 23, 2021 Issued
Array ( [id] => 19093705 [patent_doc_number] => 11955169 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-09 [patent_title] => High-speed multi-port memory supporting collision [patent_app_type] => utility [patent_app_number] => 17/210230 [patent_app_country] => US [patent_app_date] => 2021-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7929 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17210230 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/210230
High-speed multi-port memory supporting collision Mar 22, 2021 Issued
Array ( [id] => 18120360 [patent_doc_number] => 11551758 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-10 [patent_title] => Memories configured to perform concurrent access operations on different groupings of memory cells [patent_app_type] => utility [patent_app_number] => 17/206827 [patent_app_country] => US [patent_app_date] => 2021-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 20 [patent_no_of_words] => 12064 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17206827 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/206827
Memories configured to perform concurrent access operations on different groupings of memory cells Mar 18, 2021 Issued
Array ( [id] => 16936099 [patent_doc_number] => 20210201988 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-01 [patent_title] => LATCH CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/201636 [patent_app_country] => US [patent_app_date] => 2021-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9065 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17201636 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/201636
Latch circuit Mar 14, 2021 Issued
Array ( [id] => 18431441 [patent_doc_number] => 11676668 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-13 [patent_title] => Responding to changes in available power supply [patent_app_type] => utility [patent_app_number] => 17/200959 [patent_app_country] => US [patent_app_date] => 2021-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 9502 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17200959 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/200959
Responding to changes in available power supply Mar 14, 2021 Issued
Array ( [id] => 16920136 [patent_doc_number] => 20210193228 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-24 [patent_title] => MEMORY SYSTEM HAVING SEMICONDUCTOR MEMORY DEVICE THAT PERFORMS VERIFY OPERATIONS USING VARIOUS VERIFY VOLTAGES [patent_app_type] => utility [patent_app_number] => 17/196140 [patent_app_country] => US [patent_app_date] => 2021-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14211 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17196140 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/196140
Memory system having semiconductor memory device that performs verify operations using various verify voltages Mar 8, 2021 Issued
Array ( [id] => 18983321 [patent_doc_number] => 11908506 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-20 [patent_title] => Memory cell biasing techniques [patent_app_type] => utility [patent_app_number] => 17/196661 [patent_app_country] => US [patent_app_date] => 2021-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 13373 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17196661 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/196661
Memory cell biasing techniques Mar 8, 2021 Issued
Array ( [id] => 18137100 [patent_doc_number] => 11562788 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-24 [patent_title] => Memory processing unit [patent_app_type] => utility [patent_app_number] => 17/194155 [patent_app_country] => US [patent_app_date] => 2021-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4507 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17194155 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/194155
Memory processing unit Mar 4, 2021 Issued
Array ( [id] => 16904535 [patent_doc_number] => 20210183451 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-17 [patent_title] => SYSTEMS AND METHODS INVOLVING HARDWARE-BASED RESET OF UNRESPONSIVE MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 17/188153 [patent_app_country] => US [patent_app_date] => 2021-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4144 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17188153 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/188153
Systems and methods involving hardware-based reset of unresponsive memory devices Feb 28, 2021 Issued
Array ( [id] => 18578712 [patent_doc_number] => 11735251 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-22 [patent_title] => Timing control circuit of memory device with tracking word line and tracking bit line [patent_app_type] => utility [patent_app_number] => 17/182807 [patent_app_country] => US [patent_app_date] => 2021-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7797 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17182807 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/182807
Timing control circuit of memory device with tracking word line and tracking bit line Feb 22, 2021 Issued
Array ( [id] => 16811803 [patent_doc_number] => 20210134358 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-06 [patent_title] => SRAM WITH BURST MODE OPERATION [patent_app_type] => utility [patent_app_number] => 17/144077 [patent_app_country] => US [patent_app_date] => 2021-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5397 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17144077 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/144077
SRAM with burst mode operation Jan 6, 2021 Issued
Array ( [id] => 17447869 [patent_doc_number] => 20220068374 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => Systems and Methods for Improved Data Access Speed [patent_app_type] => utility [patent_app_number] => 17/141279 [patent_app_country] => US [patent_app_date] => 2021-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4041 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17141279 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/141279
Systems and methods for improved data access speed Jan 4, 2021 Issued
Array ( [id] => 19414507 [patent_doc_number] => 12080341 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-03 [patent_title] => Memory device including dual control circuits [patent_app_type] => utility [patent_app_number] => 17/141124 [patent_app_country] => US [patent_app_date] => 2021-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8088 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 310 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17141124 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/141124
Memory device including dual control circuits Jan 3, 2021 Issued
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