Search

Michael J. Zanelli

Examiner (ID: 3403, Phone: (571)272-6969 , Office: P/3661 )

Most Active Art Unit
3661
Art Unit(s)
3614, 3661, 2304, 2763, 3641
Total Applications
3349
Issued Applications
2967
Pending Applications
100
Abandoned Applications
299

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17270388 [patent_doc_number] => 11195816 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-07 [patent_title] => Integrated circuit packages comprising a plurality of redistribution structures and methods of forming the same [patent_app_type] => utility [patent_app_number] => 16/518992 [patent_app_country] => US [patent_app_date] => 2019-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 25 [patent_no_of_words] => 7940 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16518992 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/518992
Integrated circuit packages comprising a plurality of redistribution structures and methods of forming the same Jul 22, 2019 Issued
Array ( [id] => 17716751 [patent_doc_number] => 11380751 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-05 [patent_title] => Organic lighting apparatus including fuse structure [patent_app_type] => utility [patent_app_number] => 16/503159 [patent_app_country] => US [patent_app_date] => 2019-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 7158 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 320 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16503159 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/503159
Organic lighting apparatus including fuse structure Jul 2, 2019 Issued
Array ( [id] => 17048027 [patent_doc_number] => 11101217 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-24 [patent_title] => Buried power rail for transistor devices [patent_app_type] => utility [patent_app_number] => 16/455148 [patent_app_country] => US [patent_app_date] => 2019-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 20 [patent_no_of_words] => 7589 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16455148 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/455148
Buried power rail for transistor devices Jun 26, 2019 Issued
Array ( [id] => 15462373 [patent_doc_number] => 20200044011 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-06 [patent_title] => RESISTANCE ELEMENT AND MANUFACTURING METHOD OF RESISTANCE ELEMENT [patent_app_type] => utility [patent_app_number] => 16/455128 [patent_app_country] => US [patent_app_date] => 2019-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5486 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16455128 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/455128
Resistance element and manufacturing method of resistance element Jun 26, 2019 Issued
Array ( [id] => 16668590 [patent_doc_number] => 10937849 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-02 [patent_title] => Array substrate and method of manufacturing the same, display panel and display device [patent_app_type] => utility [patent_app_number] => 16/453534 [patent_app_country] => US [patent_app_date] => 2019-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 9211 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 637 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16453534 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/453534
Array substrate and method of manufacturing the same, display panel and display device Jun 25, 2019 Issued
Array ( [id] => 16172899 [patent_doc_number] => 10714477 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-14 [patent_title] => SiGe p-channel tri-gate transistor based on bulk silicon and fabrication method thereof [patent_app_type] => utility [patent_app_number] => 16/411381 [patent_app_country] => US [patent_app_date] => 2019-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 4470 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16411381 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/411381
SiGe p-channel tri-gate transistor based on bulk silicon and fabrication method thereof May 13, 2019 Issued
Array ( [id] => 14722489 [patent_doc_number] => 20190252308 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-15 [patent_title] => METHOD OF FABRICATING FIELD EFFECT TRANSISTOR HAVING NON-ORTHOGONAL GATE ELECTRODE [patent_app_type] => utility [patent_app_number] => 16/397581 [patent_app_country] => US [patent_app_date] => 2019-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4896 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16397581 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/397581
Method of fabricating field effect transistor having non-orthogonal gate electrode Apr 28, 2019 Issued
Array ( [id] => 16120257 [patent_doc_number] => 20200212151 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-02 [patent_title] => FLEXIBLE DISPLAY PANEL AND FLEXIBLE DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 16/349616 [patent_app_country] => US [patent_app_date] => 2019-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4908 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16349616 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/349616
FLEXIBLE DISPLAY PANEL AND FLEXIBLE DISPLAY DEVICE Mar 17, 2019 Abandoned
Array ( [id] => 14350953 [patent_doc_number] => 20190157449 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-23 [patent_title] => Semiconductor Device Having Contact Trenches Extending from Opposite Sides of a Semiconductor Body [patent_app_type] => utility [patent_app_number] => 16/235550 [patent_app_country] => US [patent_app_date] => 2018-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8660 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16235550 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/235550
Semiconductor Device Having Contact Trenches Extending from Opposite Sides of a Semiconductor Body Dec 27, 2018 Abandoned
Array ( [id] => 14510109 [patent_doc_number] => 20190198709 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-27 [patent_title] => III-NITRIDE MULTI-COLOR ON WAFER MICRO-LED ENABLED BY TUNNEL JUNCTIONS [patent_app_type] => utility [patent_app_number] => 16/228211 [patent_app_country] => US [patent_app_date] => 2018-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10936 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16228211 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/228211
III-NITRIDE MULTI-COLOR ON WAFER MICRO-LED ENABLED BY TUNNEL JUNCTIONS Dec 19, 2018 Abandoned
Array ( [id] => 17623373 [patent_doc_number] => 11342439 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-24 [patent_title] => III-V field effect transistor and semiconductor structure [patent_app_type] => utility [patent_app_number] => 16/228188 [patent_app_country] => US [patent_app_date] => 2018-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5558 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16228188 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/228188
III-V field effect transistor and semiconductor structure Dec 19, 2018 Issued
Array ( [id] => 17456085 [patent_doc_number] => 11270952 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-08 [patent_title] => Seal ring structure for semiconductor device [patent_app_type] => utility [patent_app_number] => 16/222355 [patent_app_country] => US [patent_app_date] => 2018-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 8803 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16222355 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/222355
Seal ring structure for semiconductor device Dec 16, 2018 Issued
Array ( [id] => 14509513 [patent_doc_number] => 20190198411 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-27 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/214284 [patent_app_country] => US [patent_app_date] => 2018-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4425 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16214284 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/214284
Folded substrate for stacked integrated circuit devices Dec 9, 2018 Issued
Array ( [id] => 16653425 [patent_doc_number] => 10930618 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-23 [patent_title] => Semiconductor package having chip stack [patent_app_type] => utility [patent_app_number] => 16/214397 [patent_app_country] => US [patent_app_date] => 2018-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7603 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16214397 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/214397
Semiconductor package having chip stack Dec 9, 2018 Issued
Array ( [id] => 14676571 [patent_doc_number] => 20190237400 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-01 [patent_title] => INTEGRATED CIRCUIT WITH METALLIC INTERLOCKING STRUCTURE [patent_app_type] => utility [patent_app_number] => 16/213709 [patent_app_country] => US [patent_app_date] => 2018-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7902 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16213709 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/213709
INTEGRATED CIRCUIT WITH METALLIC INTERLOCKING STRUCTURE Dec 6, 2018 Abandoned
Array ( [id] => 16464154 [patent_doc_number] => 10847515 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-24 [patent_title] => Semiconductor devices with nanowires and methods for fabricating the same [patent_app_type] => utility [patent_app_number] => 16/203946 [patent_app_country] => US [patent_app_date] => 2018-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 36 [patent_no_of_words] => 11049 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16203946 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/203946
Semiconductor devices with nanowires and methods for fabricating the same Nov 28, 2018 Issued
Array ( [id] => 14024715 [patent_doc_number] => 20190074351 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-07 [patent_title] => METHODS OF FABRICATING A SEMICONDUCTOR STRUCTURE INCLUDING CAPACITOR STRUCTURES [patent_app_type] => utility [patent_app_number] => 16/183463 [patent_app_country] => US [patent_app_date] => 2018-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3847 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16183463 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/183463
Methods of fabricating a decoupling capacitor in a semiconductor structure Nov 6, 2018 Issued
Array ( [id] => 14079531 [patent_doc_number] => 20190088653 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-21 [patent_title] => Memory Cells and Memory Arrays [patent_app_type] => utility [patent_app_number] => 16/183528 [patent_app_country] => US [patent_app_date] => 2018-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5562 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16183528 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/183528
Vertical 2T-2C memory cells and memory arrays Nov 6, 2018 Issued
Array ( [id] => 14079529 [patent_doc_number] => 20190088652 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-21 [patent_title] => Memory Cells and Memory Arrays [patent_app_type] => utility [patent_app_number] => 16/183468 [patent_app_country] => US [patent_app_date] => 2018-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5213 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16183468 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/183468
Vertical two-transistor single capacitor memory cells and memory arrays Nov 6, 2018 Issued
Array ( [id] => 14722847 [patent_doc_number] => 20190252487 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-15 [patent_title] => DISPLAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 16/177754 [patent_app_country] => US [patent_app_date] => 2018-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8913 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16177754 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/177754
Conductive lead arrangement for display substrate and manufacturing method thereof, and display device Oct 31, 2018 Issued
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