Michael James Carey

Array ( [id] => 6355339 [patent_doc_number] => 20100073035 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-25 [patent_title] => 'SYNCHRONOUS FREQUENCY SYNTHESIZER' [patent_app_type] => utility [patent_app_number] => 12/238189 [patent_app_country] => US [patent_app_date] => 2008-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5183 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0073/20100073035.pdf [firstpage_image] =>[orig_patent_app_number] => 12238189 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7742324 [patent_doc_number] => 08106684 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-31 [patent_title] => 'High-speed low-voltage differential signaling system' [patent_app_type] => utility [patent_app_number] => 12/236963 [patent_app_country] => US [patent_app_date] => 2008-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 10041 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/106/08106684.pdf [firstpage_image] =>[orig_patent_app_number] => 12236963 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6355420 [patent_doc_number] => 20100073048 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-25 [patent_title] => 'PHASE LOCKED LOOP AND CALIBRATION METHOD' [patent_app_type] => utility [patent_app_number] => 12/236725 [patent_app_country] => US [patent_app_date] => 2008-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3109 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0073/20100073048.pdf [firstpage_image] =>[orig_patent_app_number] => 12236725 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7531023 [patent_doc_number] => 07843248 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-11-30 [patent_title] => 'Analog switch with overcurrent detection' [patent_app_type] => utility [patent_app_number] => 12/235274 [patent_app_country] => US [patent_app_date] => 2008-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 3516 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/843/07843248.pdf [firstpage_image] =>[orig_patent_app_number] => 12235274 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15016 [patent_doc_number] => 07804339 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-28 [patent_title] => 'Serial bus interface circuit' [patent_app_type] => utility [patent_app_number] => 12/233617 [patent_app_country] => US [patent_app_date] => 2008-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2713 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 302 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/804/07804339.pdf [firstpage_image] =>[orig_patent_app_number] => 12233617 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5555 [patent_doc_number] => 07816962 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-19 [patent_title] => 'Delay locked loop with improved jitter and clock delay compensating method thereof' [patent_app_type] => utility [patent_app_number] => 12/284060 [patent_app_country] => US [patent_app_date] => 2008-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 7577 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/816/07816962.pdf [firstpage_image] =>[orig_patent_app_number] => 12284060 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 104244 [patent_doc_number] => 07724045 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-25 [patent_title] => 'Output buffer circuit' [patent_app_type] => utility [patent_app_number] => 12/211841 [patent_app_country] => US [patent_app_date] => 2008-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2540 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/724/07724045.pdf [firstpage_image] =>[orig_patent_app_number] => 12211841 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4446435 [patent_doc_number] => 07863973 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-04 [patent_title] => 'Operating panel arrangement for domestic appliances and method for manufacturing an operating panel arrangement' [patent_app_type] => utility [patent_app_number] => 12/210984 [patent_app_country] => US [patent_app_date] => 2008-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 7135 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/863/07863973.pdf [firstpage_image] =>[orig_patent_app_number] => 12210984 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 23750 [patent_doc_number] => 07800414 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-21 [patent_title] => 'Differential current driving type data transmission system' [patent_app_type] => utility [patent_app_number] => 12/209804 [patent_app_country] => US [patent_app_date] => 2008-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 3694 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/800/07800414.pdf [firstpage_image] =>[orig_patent_app_number] => 12209804 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5450363 [patent_doc_number] => 20090066399 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-12 [patent_title] => 'Level shift circuit' [patent_app_type] => utility [patent_app_number] => 12/230953 [patent_app_country] => US [patent_app_date] => 2008-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5576 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20090066399.pdf [firstpage_image] =>[orig_patent_app_number] => 12230953 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8400163 [patent_doc_number] => 08270558 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-09-18 [patent_title] => 'Electronic device, barrel shifter unit and method of barrel shifting' [patent_app_type] => utility [patent_app_number] => 12/733600 [patent_app_country] => US [patent_app_date] => 2008-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3226 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12733600 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6217075 [patent_doc_number] => 20100052738 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-04 [patent_title] => 'FREQUENCY DIVIDER FOR WIRELESS COMMUNICATION SYSTEM AND DRIVING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/200405 [patent_app_country] => US [patent_app_date] => 2008-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5168 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20100052738.pdf [firstpage_image] =>[orig_patent_app_number] => 12200405 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7998341 [patent_doc_number] => 08081018 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-12-20 [patent_title] => 'Low power radio frequency divider' [patent_app_type] => utility [patent_app_number] => 12/195733 [patent_app_country] => US [patent_app_date] => 2008-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6069 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/081/08081018.pdf [firstpage_image] =>[orig_patent_app_number] => 12195733 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4580450 [patent_doc_number] => 07825703 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-02 [patent_title] => 'Divide-by-three quadrature frequency divider' [patent_app_type] => utility [patent_app_number] => 12/193693 [patent_app_country] => US [patent_app_date] => 2008-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 5289 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/825/07825703.pdf [firstpage_image] =>[orig_patent_app_number] => 12193693 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 191505 [patent_doc_number] => 07642819 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-01-05 [patent_title] => 'High speed current mode write driver' [patent_app_type] => utility [patent_app_number] => 12/191885 [patent_app_country] => US [patent_app_date] => 2008-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4592 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/642/07642819.pdf [firstpage_image] =>[orig_patent_app_number] => 12191885 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5328407 [patent_doc_number] => 20090108884 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-30 [patent_title] => 'High Side Boosted Gate Drive Circuit' [patent_app_type] => utility [patent_app_number] => 12/190996 [patent_app_country] => US [patent_app_date] => 2008-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 7806 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0108/20090108884.pdf [firstpage_image] =>[orig_patent_app_number] => 12190996 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 152869 [patent_doc_number] => 07683683 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-03-23 [patent_title] => 'Frequency doubler with duty-cycle correction and associated methods' [patent_app_type] => utility [patent_app_number] => 12/186898 [patent_app_country] => US [patent_app_date] => 2008-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 5918 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/683/07683683.pdf [firstpage_image] =>[orig_patent_app_number] => 12186898 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6605848 [patent_doc_number] => 20100033220 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-11 [patent_title] => 'ACCUMULATED PHASE-TO-DIGITAL CONVERSION IN DIGITAL PHASE LOCKED LOOPS' [patent_app_type] => utility [patent_app_number] => 12/187321 [patent_app_country] => US [patent_app_date] => 2008-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5018 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0033/20100033220.pdf [firstpage_image] =>[orig_patent_app_number] => 12187321 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8190705 [patent_doc_number] => 08183894 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-22 [patent_title] => 'Device for and a method of generating signals' [patent_app_type] => utility [patent_app_number] => 12/674735 [patent_app_country] => US [patent_app_date] => 2008-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 5526 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/183/08183894.pdf [firstpage_image] =>[orig_patent_app_number] => 12674735 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7597124 [patent_doc_number] => 07619454 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-11-17 [patent_title] => 'Clock generator for semiconductor memory apparatus' [patent_app_type] => utility [patent_app_number] => 12/185855 [patent_app_country] => US [patent_app_date] => 2008-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3298 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/619/07619454.pdf [firstpage_image] =>[orig_patent_app_number] => 12185855 [rel_patent_id] =>[rel_patent_doc_number] =>)