Search

Michael James Carey

Examiner (ID: 835)

Most Active Art Unit
3766
Art Unit(s)
3762, 4187, 3766, 3795, 3792
Total Applications
666
Issued Applications
554
Pending Applications
26
Abandoned Applications
95

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 104245 [patent_doc_number] => 07724046 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-25 [patent_title] => 'High side/low side driver device for switching electrical loads' [patent_app_type] => utility [patent_app_number] => 11/752296 [patent_app_country] => US [patent_app_date] => 2007-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 20 [patent_no_of_words] => 11515 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/724/07724046.pdf [firstpage_image] =>[orig_patent_app_number] => 11752296 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/752296
High side/low side driver device for switching electrical loads May 21, 2007 Issued
Array ( [id] => 93610 [patent_doc_number] => 07737752 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-15 [patent_title] => 'Techniques for integrated circuit clock management' [patent_app_type] => utility [patent_app_number] => 11/750267 [patent_app_country] => US [patent_app_date] => 2007-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 6799 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/737/07737752.pdf [firstpage_image] =>[orig_patent_app_number] => 11750267 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/750267
Techniques for integrated circuit clock management May 16, 2007 Issued
Array ( [id] => 5083359 [patent_doc_number] => 20070273410 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-29 [patent_title] => 'Clock switching circuit' [patent_app_type] => utility [patent_app_number] => 11/798091 [patent_app_country] => US [patent_app_date] => 2007-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8968 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0273/20070273410.pdf [firstpage_image] =>[orig_patent_app_number] => 11798091 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/798091
Clock switching circuit May 9, 2007 Issued
Array ( [id] => 5223366 [patent_doc_number] => 20070252632 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-01 [patent_title] => 'Clock distribution circuit, semiconductor integrated circuit, and clock distribution method' [patent_app_type] => utility [patent_app_number] => 11/790342 [patent_app_country] => US [patent_app_date] => 2007-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3620 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0252/20070252632.pdf [firstpage_image] =>[orig_patent_app_number] => 11790342 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/790342
Clock distribution circuit Apr 24, 2007 Issued
Array ( [id] => 331056 [patent_doc_number] => 07511555 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-31 [patent_title] => 'Level conversion circuit and input-output device using same' [patent_app_type] => utility [patent_app_number] => 11/790335 [patent_app_country] => US [patent_app_date] => 2007-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 9606 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/511/07511555.pdf [firstpage_image] =>[orig_patent_app_number] => 11790335 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/790335
Level conversion circuit and input-output device using same Apr 24, 2007 Issued
Array ( [id] => 592771 [patent_doc_number] => 07439790 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-21 [patent_title] => 'Level shifter circuit' [patent_app_type] => utility [patent_app_number] => 11/790198 [patent_app_country] => US [patent_app_date] => 2007-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3467 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 367 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/439/07439790.pdf [firstpage_image] =>[orig_patent_app_number] => 11790198 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/790198
Level shifter circuit Apr 23, 2007 Issued
Array ( [id] => 304136 [patent_doc_number] => 07535277 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-19 [patent_title] => 'Frequency dividing phase shift circuit' [patent_app_type] => utility [patent_app_number] => 11/783656 [patent_app_country] => US [patent_app_date] => 2007-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 22 [patent_no_of_words] => 6651 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/535/07535277.pdf [firstpage_image] =>[orig_patent_app_number] => 11783656 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/783656
Frequency dividing phase shift circuit Apr 10, 2007 Issued
Array ( [id] => 349380 [patent_doc_number] => 07495499 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-24 [patent_title] => 'Power transistor circuit and the method thereof' [patent_app_type] => utility [patent_app_number] => 11/783556 [patent_app_country] => US [patent_app_date] => 2007-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 1790 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/495/07495499.pdf [firstpage_image] =>[orig_patent_app_number] => 11783556 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/783556
Power transistor circuit and the method thereof Apr 9, 2007 Issued
Array ( [id] => 5123986 [patent_doc_number] => 20070236257 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-11 [patent_title] => 'Debounce circuit and method' [patent_app_type] => utility [patent_app_number] => 11/783579 [patent_app_country] => US [patent_app_date] => 2007-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 17336 [patent_no_of_claims] => 59 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0236/20070236257.pdf [firstpage_image] =>[orig_patent_app_number] => 11783579 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/783579
Debounce circuit and method Apr 9, 2007 Issued
Array ( [id] => 334827 [patent_doc_number] => 07508240 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-03-24 [patent_title] => 'Power mains zero-crossing detector' [patent_app_type] => utility [patent_app_number] => 11/784577 [patent_app_country] => US [patent_app_date] => 2007-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 825 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/508/07508240.pdf [firstpage_image] =>[orig_patent_app_number] => 11784577 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/784577
Power mains zero-crossing detector Apr 5, 2007 Issued
Array ( [id] => 5123484 [patent_doc_number] => 20070235754 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-11 [patent_title] => 'Electronic switch circuit' [patent_app_type] => utility [patent_app_number] => 11/783082 [patent_app_country] => US [patent_app_date] => 2007-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2993 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0235/20070235754.pdf [firstpage_image] =>[orig_patent_app_number] => 11783082 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/783082
Electronic switch circuit Apr 4, 2007 Abandoned
Array ( [id] => 6305363 [patent_doc_number] => 20100069030 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-18 [patent_title] => 'FREQUENCY MEASURING BROADBAND DIGITAL RECEIVER' [patent_app_type] => utility [patent_app_number] => 12/278300 [patent_app_country] => US [patent_app_date] => 2007-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4872 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0069/20100069030.pdf [firstpage_image] =>[orig_patent_app_number] => 12278300 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/278300
Frequency measuring broadband digital receiver Jan 21, 2007 Issued
Array ( [id] => 4518857 [patent_doc_number] => 07932755 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-26 [patent_title] => 'Phase synchronization for wide area integrated circuits' [patent_app_type] => utility [patent_app_number] => 11/620309 [patent_app_country] => US [patent_app_date] => 2007-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3520 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/932/07932755.pdf [firstpage_image] =>[orig_patent_app_number] => 11620309 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/620309
Phase synchronization for wide area integrated circuits Jan 4, 2007 Issued
Array ( [id] => 4877206 [patent_doc_number] => 20080150589 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-26 [patent_title] => 'SYSTEMS AND METHODS FOR MULTIPLE EQUATION GRAPHING' [patent_app_type] => utility [patent_app_number] => 11/613344 [patent_app_country] => US [patent_app_date] => 2006-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4567 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0150/20080150589.pdf [firstpage_image] =>[orig_patent_app_number] => 11613344 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/613344
Systems and methods for hysteresis control in a comparator Dec 19, 2006 Issued
Array ( [id] => 5020056 [patent_doc_number] => 20070146022 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-28 [patent_title] => 'ANALOG FREQUENCY DIVIDER' [patent_app_type] => utility [patent_app_number] => 11/612151 [patent_app_country] => US [patent_app_date] => 2006-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3922 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0146/20070146022.pdf [firstpage_image] =>[orig_patent_app_number] => 11612151 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/612151
ANALOG FREQUENCY DIVIDER Dec 17, 2006 Abandoned
Array ( [id] => 4821561 [patent_doc_number] => 20080122551 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-29 [patent_title] => 'APPARATUS FOR PULSE WIDTH MODULATION AND METHOD FOR CONTROLLING THEREOF' [patent_app_type] => utility [patent_app_number] => 11/609908 [patent_app_country] => US [patent_app_date] => 2006-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7370 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0122/20080122551.pdf [firstpage_image] =>[orig_patent_app_number] => 11609908 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/609908
APPARATUS FOR PULSE WIDTH MODULATION AND METHOD FOR CONTROLLING THEREOF Dec 12, 2006 Abandoned
Array ( [id] => 4783171 [patent_doc_number] => 20080136500 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-12 [patent_title] => 'CHARGE PUMP FOR GENERATION OF MULTIPLE OUTPUT-VOLTAGE LEVELS' [patent_app_type] => utility [patent_app_number] => 11/608941 [patent_app_country] => US [patent_app_date] => 2006-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3704 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0136/20080136500.pdf [firstpage_image] =>[orig_patent_app_number] => 11608941 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/608941
Charge pump for generation of multiple output-voltage levels Dec 10, 2006 Issued
Array ( [id] => 821056 [patent_doc_number] => 07408391 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-08-05 [patent_title] => 'Charge pump for PLL/DLL' [patent_app_type] => utility [patent_app_number] => 11/636876 [patent_app_country] => US [patent_app_date] => 2006-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5954 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/408/07408391.pdf [firstpage_image] =>[orig_patent_app_number] => 11636876 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/636876
Charge pump for PLL/DLL Dec 10, 2006 Issued
Array ( [id] => 271061 [patent_doc_number] => 07564298 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-21 [patent_title] => 'Voltage reference circuit and current reference circuit using vertical bipolar junction transistor implemented by deep n-well CMOS process' [patent_app_type] => utility [patent_app_number] => 11/608279 [patent_app_country] => US [patent_app_date] => 2006-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 3790 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/564/07564298.pdf [firstpage_image] =>[orig_patent_app_number] => 11608279 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/608279
Voltage reference circuit and current reference circuit using vertical bipolar junction transistor implemented by deep n-well CMOS process Dec 7, 2006 Issued
Array ( [id] => 814175 [patent_doc_number] => 07414451 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-08-19 [patent_title] => 'Clock generator for semiconductor memory apparatus' [patent_app_type] => utility [patent_app_number] => 11/605463 [patent_app_country] => US [patent_app_date] => 2006-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3468 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/414/07414451.pdf [firstpage_image] =>[orig_patent_app_number] => 11605463 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/605463
Clock generator for semiconductor memory apparatus Nov 28, 2006 Issued
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