Search

Michael James Carey

Examiner (ID: 835)

Most Active Art Unit
3766
Art Unit(s)
3762, 4187, 3766, 3795, 3792
Total Applications
666
Issued Applications
554
Pending Applications
26
Abandoned Applications
95

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 412170 [patent_doc_number] => 07282973 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-10-16 [patent_title] => 'Enhanced DLL phase output scheme' [patent_app_type] => utility [patent_app_number] => 11/297040 [patent_app_country] => US [patent_app_date] => 2005-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5054 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/282/07282973.pdf [firstpage_image] =>[orig_patent_app_number] => 11297040 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/297040
Enhanced DLL phase output scheme Dec 6, 2005 Issued
Array ( [id] => 5838923 [patent_doc_number] => 20060119404 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-08 [patent_title] => 'Phase locked loop circuit' [patent_app_type] => utility [patent_app_number] => 11/294383 [patent_app_country] => US [patent_app_date] => 2005-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4801 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20060119404.pdf [firstpage_image] =>[orig_patent_app_number] => 11294383 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/294383
Phase locked loop circuit Dec 5, 2005 Abandoned
Array ( [id] => 5234327 [patent_doc_number] => 20070126482 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-07 [patent_title] => 'Highest supply selection circuit' [patent_app_type] => utility [patent_app_number] => 11/296777 [patent_app_country] => US [patent_app_date] => 2005-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2526 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0126/20070126482.pdf [firstpage_image] =>[orig_patent_app_number] => 11296777 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/296777
Highest supply selection circuit Dec 5, 2005 Issued
Array ( [id] => 5670737 [patent_doc_number] => 20060176091 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-10 [patent_title] => 'Delay locked loop circuit' [patent_app_type] => utility [patent_app_number] => 11/289753 [patent_app_country] => US [patent_app_date] => 2005-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6842 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0176/20060176091.pdf [firstpage_image] =>[orig_patent_app_number] => 11289753 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/289753
Delay locked loop circuit Nov 29, 2005 Abandoned
Array ( [id] => 444086 [patent_doc_number] => 07256626 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-08-14 [patent_title] => 'Low-voltage differential signal driver with pre-emphasis circuit' [patent_app_type] => utility [patent_app_number] => 11/164405 [patent_app_country] => US [patent_app_date] => 2005-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5656 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 361 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/256/07256626.pdf [firstpage_image] =>[orig_patent_app_number] => 11164405 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/164405
Low-voltage differential signal driver with pre-emphasis circuit Nov 21, 2005 Issued
Array ( [id] => 5746109 [patent_doc_number] => 20060109039 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-25 [patent_title] => 'Pulse width modulation device with a power saving mode controlled by an output voltage feedback hysteresis circuit' [patent_app_type] => utility [patent_app_number] => 11/282585 [patent_app_country] => US [patent_app_date] => 2005-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3706 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20060109039.pdf [firstpage_image] =>[orig_patent_app_number] => 11282585 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/282585
Pulse width modulation device with a power saving mode controlled by an output voltage feedback hysteresis circuit Nov 20, 2005 Issued
Array ( [id] => 5152079 [patent_doc_number] => 20070034961 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-15 [patent_title] => 'Semiconductor device, display device, and electronic device' [patent_app_type] => utility [patent_app_number] => 11/282469 [patent_app_country] => US [patent_app_date] => 2005-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 16261 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0034/20070034961.pdf [firstpage_image] =>[orig_patent_app_number] => 11282469 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/282469
Level shifter for display device Nov 20, 2005 Issued
Array ( [id] => 5192260 [patent_doc_number] => 20070080742 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-12 [patent_title] => 'System and method for switching between high voltage and low voltage' [patent_app_type] => utility [patent_app_number] => 11/283061 [patent_app_country] => US [patent_app_date] => 2005-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4943 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0080/20070080742.pdf [firstpage_image] =>[orig_patent_app_number] => 11283061 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/283061
System and method for switching between high voltage and low voltage Nov 16, 2005 Issued
Array ( [id] => 4969022 [patent_doc_number] => 20070109024 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-17 [patent_title] => 'Latch type sense amplifier' [patent_app_type] => utility [patent_app_number] => 11/281180 [patent_app_country] => US [patent_app_date] => 2005-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4269 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20070109024.pdf [firstpage_image] =>[orig_patent_app_number] => 11281180 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/281180
Latch type sense amplifier Nov 16, 2005 Issued
Array ( [id] => 5774793 [patent_doc_number] => 20060103433 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-18 [patent_title] => 'Voltage comparator circuit with symmetric circuit topology' [patent_app_type] => utility [patent_app_number] => 11/274183 [patent_app_country] => US [patent_app_date] => 2005-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 15009 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0103/20060103433.pdf [firstpage_image] =>[orig_patent_app_number] => 11274183 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/274183
Voltage comparator circuit with symmetric circuit topology Nov 15, 2005 Issued
Array ( [id] => 5653342 [patent_doc_number] => 20060139077 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-29 [patent_title] => 'Flip-flop circuit' [patent_app_type] => utility [patent_app_number] => 11/274298 [patent_app_country] => US [patent_app_date] => 2005-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 17265 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0139/20060139077.pdf [firstpage_image] =>[orig_patent_app_number] => 11274298 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/274298
Flip-flop circuit including latch circuits Nov 15, 2005 Issued
Array ( [id] => 4640240 [patent_doc_number] => 08018268 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-09-13 [patent_title] => 'Over-voltage tolerant input circuit' [patent_app_type] => utility [patent_app_number] => 11/273825 [patent_app_country] => US [patent_app_date] => 2005-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2907 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/018/08018268.pdf [firstpage_image] =>[orig_patent_app_number] => 11273825 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/273825
Over-voltage tolerant input circuit Nov 14, 2005 Issued
Array ( [id] => 5863637 [patent_doc_number] => 20060097767 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-11 [patent_title] => 'Clock signal generator and method thereof' [patent_app_type] => utility [patent_app_number] => 11/268505 [patent_app_country] => US [patent_app_date] => 2005-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2145 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0097/20060097767.pdf [firstpage_image] =>[orig_patent_app_number] => 11268505 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/268505
Clock signal generator with self-calibrating mode Nov 7, 2005 Issued
Array ( [id] => 458361 [patent_doc_number] => 07245172 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-17 [patent_title] => 'Level shifter apparatus and method for minimizing duty cycle distortion' [patent_app_type] => utility [patent_app_number] => 11/269245 [patent_app_country] => US [patent_app_date] => 2005-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 6031 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/245/07245172.pdf [firstpage_image] =>[orig_patent_app_number] => 11269245 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/269245
Level shifter apparatus and method for minimizing duty cycle distortion Nov 7, 2005 Issued
Array ( [id] => 465889 [patent_doc_number] => 07239188 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-07-03 [patent_title] => 'Locked-loop integrated circuits having speed tracking circuits therein' [patent_app_type] => utility [patent_app_number] => 11/264111 [patent_app_country] => US [patent_app_date] => 2005-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3337 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/239/07239188.pdf [firstpage_image] =>[orig_patent_app_number] => 11264111 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/264111
Locked-loop integrated circuits having speed tracking circuits therein Oct 31, 2005 Issued
Array ( [id] => 429175 [patent_doc_number] => 07268613 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-11 [patent_title] => 'Transistor switch with integral body connection to prevent latchup' [patent_app_type] => utility [patent_app_number] => 11/263008 [patent_app_country] => US [patent_app_date] => 2005-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 3866 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/268/07268613.pdf [firstpage_image] =>[orig_patent_app_number] => 11263008 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/263008
Transistor switch with integral body connection to prevent latchup Oct 30, 2005 Issued
Array ( [id] => 5774806 [patent_doc_number] => 20060103446 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-18 [patent_title] => 'Driver circuit' [patent_app_type] => utility [patent_app_number] => 11/260506 [patent_app_country] => US [patent_app_date] => 2005-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8725 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0103/20060103446.pdf [firstpage_image] =>[orig_patent_app_number] => 11260506 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/260506
Driver circuit with reduced jitter between circuit domains Oct 26, 2005 Issued
Array ( [id] => 436393 [patent_doc_number] => 07262651 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-08-28 [patent_title] => 'Differential input buffer circuit with rail-to-rail input range' [patent_app_type] => utility [patent_app_number] => 11/258958 [patent_app_country] => US [patent_app_date] => 2005-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 7830 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/262/07262651.pdf [firstpage_image] =>[orig_patent_app_number] => 11258958 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/258958
Differential input buffer circuit with rail-to-rail input range Oct 25, 2005 Issued
Array ( [id] => 5346686 [patent_doc_number] => 20090002047 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-01 [patent_title] => 'Switching Circuit Which Is Used To Obtain A Doubled Dynamic Range' [patent_app_type] => utility [patent_app_number] => 11/667840 [patent_app_country] => US [patent_app_date] => 2005-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3870 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20090002047.pdf [firstpage_image] =>[orig_patent_app_number] => 11667840 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/667840
Switching circuit which is used to obtain a doubled dynamic range Oct 25, 2005 Issued
Array ( [id] => 5863630 [patent_doc_number] => 20060097760 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-11 [patent_title] => 'Differential signal generating circuit, differential signal transmitting circuit and differential signal transceiver system' [patent_app_type] => utility [patent_app_number] => 11/258024 [patent_app_country] => US [patent_app_date] => 2005-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4206 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0097/20060097760.pdf [firstpage_image] =>[orig_patent_app_number] => 11258024 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/258024
Differential signal generating circuit, differential signal transmitting circuit and differential signal transceiver system Oct 25, 2005 Abandoned
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