
Michael James Carey
Examiner (ID: 835)
| Most Active Art Unit | 3766 |
| Art Unit(s) | 3762, 4187, 3766, 3795, 3792 |
| Total Applications | 666 |
| Issued Applications | 554 |
| Pending Applications | 26 |
| Abandoned Applications | 95 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 412170
[patent_doc_number] => 07282973
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-10-16
[patent_title] => 'Enhanced DLL phase output scheme'
[patent_app_type] => utility
[patent_app_number] => 11/297040
[patent_app_country] => US
[patent_app_date] => 2005-12-07
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[pdf_file] => patents/07/282/07282973.pdf
[firstpage_image] =>[orig_patent_app_number] => 11297040
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/297040 | Enhanced DLL phase output scheme | Dec 6, 2005 | Issued |
Array
(
[id] => 5838923
[patent_doc_number] => 20060119404
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-06-08
[patent_title] => 'Phase locked loop circuit'
[patent_app_type] => utility
[patent_app_number] => 11/294383
[patent_app_country] => US
[patent_app_date] => 2005-12-06
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[firstpage_image] =>[orig_patent_app_number] => 11294383
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/294383 | Phase locked loop circuit | Dec 5, 2005 | Abandoned |
Array
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[patent_doc_number] => 20070126482
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[patent_kind] => A1
[patent_issue_date] => 2007-06-07
[patent_title] => 'Highest supply selection circuit'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/296777 | Highest supply selection circuit | Dec 5, 2005 | Issued |
Array
(
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[patent_doc_number] => 20060176091
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-08-10
[patent_title] => 'Delay locked loop circuit'
[patent_app_type] => utility
[patent_app_number] => 11/289753
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[patent_app_date] => 2005-11-30
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[firstpage_image] =>[orig_patent_app_number] => 11289753
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/289753 | Delay locked loop circuit | Nov 29, 2005 | Abandoned |
Array
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[id] => 444086
[patent_doc_number] => 07256626
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[patent_kind] => B2
[patent_issue_date] => 2007-08-14
[patent_title] => 'Low-voltage differential signal driver with pre-emphasis circuit'
[patent_app_type] => utility
[patent_app_number] => 11/164405
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/164405 | Low-voltage differential signal driver with pre-emphasis circuit | Nov 21, 2005 | Issued |
Array
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[patent_doc_number] => 20060109039
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[patent_issue_date] => 2006-05-25
[patent_title] => 'Pulse width modulation device with a power saving mode controlled by an output voltage feedback hysteresis circuit'
[patent_app_type] => utility
[patent_app_number] => 11/282585
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/282585 | Pulse width modulation device with a power saving mode controlled by an output voltage feedback hysteresis circuit | Nov 20, 2005 | Issued |
Array
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[patent_doc_number] => 20070034961
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[patent_title] => 'Semiconductor device, display device, and electronic device'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/282469 | Level shifter for display device | Nov 20, 2005 | Issued |
Array
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[id] => 5192260
[patent_doc_number] => 20070080742
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[patent_kind] => A1
[patent_issue_date] => 2007-04-12
[patent_title] => 'System and method for switching between high voltage and low voltage'
[patent_app_type] => utility
[patent_app_number] => 11/283061
[patent_app_country] => US
[patent_app_date] => 2005-11-16
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/283061 | System and method for switching between high voltage and low voltage | Nov 16, 2005 | Issued |
Array
(
[id] => 4969022
[patent_doc_number] => 20070109024
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[patent_issue_date] => 2007-05-17
[patent_title] => 'Latch type sense amplifier'
[patent_app_type] => utility
[patent_app_number] => 11/281180
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/281180 | Latch type sense amplifier | Nov 16, 2005 | Issued |
Array
(
[id] => 5774793
[patent_doc_number] => 20060103433
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[patent_title] => 'Voltage comparator circuit with symmetric circuit topology'
[patent_app_type] => utility
[patent_app_number] => 11/274183
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[firstpage_image] =>[orig_patent_app_number] => 11274183
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/274183 | Voltage comparator circuit with symmetric circuit topology | Nov 15, 2005 | Issued |
Array
(
[id] => 5653342
[patent_doc_number] => 20060139077
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[patent_title] => 'Flip-flop circuit'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/274298 | Flip-flop circuit including latch circuits | Nov 15, 2005 | Issued |
Array
(
[id] => 4640240
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/273825 | Over-voltage tolerant input circuit | Nov 14, 2005 | Issued |
Array
(
[id] => 5863637
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[patent_title] => 'Clock signal generator and method thereof'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/268505 | Clock signal generator with self-calibrating mode | Nov 7, 2005 | Issued |
Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/263008 | Transistor switch with integral body connection to prevent latchup | Oct 30, 2005 | Issued |
Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/260506 | Driver circuit with reduced jitter between circuit domains | Oct 26, 2005 | Issued |
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/258024 | Differential signal generating circuit, differential signal transmitting circuit and differential signal transceiver system | Oct 25, 2005 | Abandoned |