Search

Michael James Carey

Examiner (ID: 835)

Most Active Art Unit
3766
Art Unit(s)
3762, 4187, 3766, 3795, 3792
Total Applications
666
Issued Applications
554
Pending Applications
26
Abandoned Applications
95

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 271045 [patent_doc_number] => 07564282 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-21 [patent_title] => 'Bistable flip-flop having retention circuit for storing state in inactive mode' [patent_app_type] => utility [patent_app_number] => 11/258826 [patent_app_country] => US [patent_app_date] => 2005-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4014 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/564/07564282.pdf [firstpage_image] =>[orig_patent_app_number] => 11258826 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/258826
Bistable flip-flop having retention circuit for storing state in inactive mode Oct 25, 2005 Issued
Array ( [id] => 926045 [patent_doc_number] => 07317343 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-01-08 [patent_title] => 'Pulse-generation circuit with multi-delay block and set-reset latches' [patent_app_type] => utility [patent_app_number] => 11/257641 [patent_app_country] => US [patent_app_date] => 2005-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 3896 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 307 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/317/07317343.pdf [firstpage_image] =>[orig_patent_app_number] => 11257641 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/257641
Pulse-generation circuit with multi-delay block and set-reset latches Oct 24, 2005 Issued
Array ( [id] => 415754 [patent_doc_number] => 07279940 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-10-09 [patent_title] => 'Switched-capacitor circuit with time-shifted switching scheme' [patent_app_type] => utility [patent_app_number] => 11/258686 [patent_app_country] => US [patent_app_date] => 2005-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 5091 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/279/07279940.pdf [firstpage_image] =>[orig_patent_app_number] => 11258686 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/258686
Switched-capacitor circuit with time-shifted switching scheme Oct 24, 2005 Issued
Array ( [id] => 857760 [patent_doc_number] => 07375575 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-05-20 [patent_title] => 'Method and apparatus for controlled voltage level shifting' [patent_app_type] => utility [patent_app_number] => 11/254601 [patent_app_country] => US [patent_app_date] => 2005-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5491 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/375/07375575.pdf [firstpage_image] =>[orig_patent_app_number] => 11254601 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/254601
Method and apparatus for controlled voltage level shifting Oct 18, 2005 Issued
Array ( [id] => 409124 [patent_doc_number] => 07285988 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-23 [patent_title] => 'Comparator circuit with offset control' [patent_app_type] => utility [patent_app_number] => 11/242020 [patent_app_country] => US [patent_app_date] => 2005-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 8011 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/285/07285988.pdf [firstpage_image] =>[orig_patent_app_number] => 11242020 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/242020
Comparator circuit with offset control Oct 3, 2005 Issued
Array ( [id] => 432823 [patent_doc_number] => 07265600 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-04 [patent_title] => 'Level shifter system and method to minimize duty cycle error due to voltage differences across power domains' [patent_app_type] => utility [patent_app_number] => 11/242670 [patent_app_country] => US [patent_app_date] => 2005-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5058 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/265/07265600.pdf [firstpage_image] =>[orig_patent_app_number] => 11242670 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/242670
Level shifter system and method to minimize duty cycle error due to voltage differences across power domains Oct 3, 2005 Issued
Array ( [id] => 4769311 [patent_doc_number] => 20080054969 [patent_country] => US [patent_kind] => A2 [patent_issue_date] => 2008-03-06 [patent_title] => 'OUTPUT DRIVER WITH SLEW RATE CONTROL' [patent_app_type] => utility [patent_app_number] => 11/241233 [patent_app_country] => US [patent_app_date] => 2005-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2250 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A2/0054/20080054969.pdf [firstpage_image] =>[orig_patent_app_number] => 11241233 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/241233
Output driver with slew rate control Sep 29, 2005 Issued
Array ( [id] => 4769311 [patent_doc_number] => 20080054969 [patent_country] => US [patent_kind] => A2 [patent_issue_date] => 2008-03-06 [patent_title] => 'OUTPUT DRIVER WITH SLEW RATE CONTROL' [patent_app_type] => utility [patent_app_number] => 11/241233 [patent_app_country] => US [patent_app_date] => 2005-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2250 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A2/0054/20080054969.pdf [firstpage_image] =>[orig_patent_app_number] => 11241233 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/241233
Output driver with slew rate control Sep 29, 2005 Issued
Array ( [id] => 5181126 [patent_doc_number] => 20070052468 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-08 [patent_title] => 'Shift down level shifter' [patent_app_type] => utility [patent_app_number] => 11/219465 [patent_app_country] => US [patent_app_date] => 2005-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1573 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20070052468.pdf [firstpage_image] =>[orig_patent_app_number] => 11219465 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/219465
Shift down level shifter Sep 1, 2005 Abandoned
Array ( [id] => 454305 [patent_doc_number] => 07248095 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-24 [patent_title] => 'Bus driver with well voltage control section' [patent_app_type] => utility [patent_app_number] => 11/213779 [patent_app_country] => US [patent_app_date] => 2005-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 21 [patent_no_of_words] => 8639 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/248/07248095.pdf [firstpage_image] =>[orig_patent_app_number] => 11213779 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/213779
Bus driver with well voltage control section Aug 29, 2005 Issued
Array ( [id] => 415774 [patent_doc_number] => 07279960 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-10-09 [patent_title] => 'Reference voltage generation using compensation current method' [patent_app_type] => utility [patent_app_number] => 11/215174 [patent_app_country] => US [patent_app_date] => 2005-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4592 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/279/07279960.pdf [firstpage_image] =>[orig_patent_app_number] => 11215174 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/215174
Reference voltage generation using compensation current method Aug 29, 2005 Issued
Array ( [id] => 5146284 [patent_doc_number] => 20070046338 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-01 [patent_title] => 'Buffer circuit with multiple voltage range' [patent_app_type] => utility [patent_app_number] => 11/215663 [patent_app_country] => US [patent_app_date] => 2005-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6630 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20070046338.pdf [firstpage_image] =>[orig_patent_app_number] => 11215663 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/215663
Buffer circuit with multiple voltage range Aug 29, 2005 Issued
Array ( [id] => 5724684 [patent_doc_number] => 20060055444 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-16 [patent_title] => 'Clock buffer circuit' [patent_app_type] => utility [patent_app_number] => 11/210757 [patent_app_country] => US [patent_app_date] => 2005-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3791 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20060055444.pdf [firstpage_image] =>[orig_patent_app_number] => 11210757 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/210757
Clock buffer circuit having predetermined gain with bias circuit thereof Aug 24, 2005 Issued
Array ( [id] => 5294306 [patent_doc_number] => 20090009232 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-08 [patent_title] => 'Power Switches' [patent_app_type] => utility [patent_app_number] => 11/664801 [patent_app_country] => US [patent_app_date] => 2005-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1298 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0009/20090009232.pdf [firstpage_image] =>[orig_patent_app_number] => 11664801 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/664801
Power Switches Aug 23, 2005 Abandoned
Array ( [id] => 881659 [patent_doc_number] => 07355456 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-08 [patent_title] => 'Wide linear range peak detector' [patent_app_type] => utility [patent_app_number] => 11/199493 [patent_app_country] => US [patent_app_date] => 2005-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5285 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/355/07355456.pdf [firstpage_image] =>[orig_patent_app_number] => 11199493 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/199493
Wide linear range peak detector Aug 7, 2005 Issued
Array ( [id] => 5878693 [patent_doc_number] => 20060028248 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-09 [patent_title] => 'Voltage comparator' [patent_app_type] => utility [patent_app_number] => 11/196415 [patent_app_country] => US [patent_app_date] => 2005-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3667 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0028/20060028248.pdf [firstpage_image] =>[orig_patent_app_number] => 11196415 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/196415
Voltage comparator utilizing voltage to current conversion Aug 3, 2005 Issued
Array ( [id] => 5049489 [patent_doc_number] => 20070030033 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-08 [patent_title] => 'Fast peak detector circuit' [patent_app_type] => utility [patent_app_number] => 11/196196 [patent_app_country] => US [patent_app_date] => 2005-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1669 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0030/20070030033.pdf [firstpage_image] =>[orig_patent_app_number] => 11196196 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/196196
Fast peak detector circuit Aug 3, 2005 Abandoned
Array ( [id] => 390777 [patent_doc_number] => 07301373 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-11-27 [patent_title] => 'Asymmetric precharged flip flop' [patent_app_type] => utility [patent_app_number] => 11/197706 [patent_app_country] => US [patent_app_date] => 2005-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3123 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/301/07301373.pdf [firstpage_image] =>[orig_patent_app_number] => 11197706 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/197706
Asymmetric precharged flip flop Aug 3, 2005 Issued
Array ( [id] => 853804 [patent_doc_number] => 07378898 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-05-27 [patent_title] => 'Voltage droop suppressing circuit' [patent_app_type] => utility [patent_app_number] => 11/195554 [patent_app_country] => US [patent_app_date] => 2005-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 2981 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/378/07378898.pdf [firstpage_image] =>[orig_patent_app_number] => 11195554 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/195554
Voltage droop suppressing circuit Aug 2, 2005 Issued
Array ( [id] => 5774803 [patent_doc_number] => 20060103443 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-18 [patent_title] => 'Clocked state devices including master-slave terminal transmission gates and methods of operating same' [patent_app_type] => utility [patent_app_number] => 11/194272 [patent_app_country] => US [patent_app_date] => 2005-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3591 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0103/20060103443.pdf [firstpage_image] =>[orig_patent_app_number] => 11194272 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/194272
Clocked state devices including master-slave terminal transmission gates and methods of operating same Jul 31, 2005 Issued
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