Search

Michael James Carey

Examiner (ID: 835)

Most Active Art Unit
3766
Art Unit(s)
3762, 4187, 3766, 3795, 3792
Total Applications
666
Issued Applications
554
Pending Applications
26
Abandoned Applications
95

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7170032 [patent_doc_number] => 20050122156 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-09 [patent_title] => 'Level-shifting circuitry having \"high\" output impedance during disable mode' [patent_app_type] => utility [patent_app_number] => 11/041464 [patent_app_country] => US [patent_app_date] => 2005-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2316 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0122/20050122156.pdf [firstpage_image] =>[orig_patent_app_number] => 11041464 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/041464
Level-shifting circuitry having “high” output impedance during disable mode Jan 23, 2005 Issued
Array ( [id] => 401834 [patent_doc_number] => 07292071 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-11-06 [patent_title] => 'Method and circuit for sampling/holding a signal' [patent_app_type] => utility [patent_app_number] => 10/905805 [patent_app_country] => US [patent_app_date] => 2005-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3895 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/292/07292071.pdf [firstpage_image] =>[orig_patent_app_number] => 10905805 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/905805
Method and circuit for sampling/holding a signal Jan 20, 2005 Issued
Array ( [id] => 401834 [patent_doc_number] => 07292071 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-11-06 [patent_title] => 'Method and circuit for sampling/holding a signal' [patent_app_type] => utility [patent_app_number] => 10/905805 [patent_app_country] => US [patent_app_date] => 2005-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3895 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/292/07292071.pdf [firstpage_image] =>[orig_patent_app_number] => 10905805 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/905805
Method and circuit for sampling/holding a signal Jan 20, 2005 Issued
Array ( [id] => 532365 [patent_doc_number] => 07183838 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-27 [patent_title] => 'Semiconductor device having internal power supply voltage dropping circuit' [patent_app_type] => utility [patent_app_number] => 11/029369 [patent_app_country] => US [patent_app_date] => 2005-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 6801 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/183/07183838.pdf [firstpage_image] =>[orig_patent_app_number] => 11029369 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/029369
Semiconductor device having internal power supply voltage dropping circuit Jan 5, 2005 Issued
Array ( [id] => 6932634 [patent_doc_number] => 20050283669 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-22 [patent_title] => 'Edge detect circuit for performance counter' [patent_app_type] => utility [patent_app_number] => 11/022021 [patent_app_country] => US [patent_app_date] => 2004-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5535 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0283/20050283669.pdf [firstpage_image] =>[orig_patent_app_number] => 11022021 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/022021
Edge detect circuit for performance counter Dec 22, 2004 Abandoned
Array ( [id] => 5915 [patent_doc_number] => 07812649 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-12 [patent_title] => 'Low power, power on reset circuit with accurate supply voltage detection' [patent_app_type] => utility [patent_app_number] => 11/015632 [patent_app_country] => US [patent_app_date] => 2004-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 1246 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/812/07812649.pdf [firstpage_image] =>[orig_patent_app_number] => 11015632 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/015632
Low power, power on reset circuit with accurate supply voltage detection Dec 16, 2004 Issued
Array ( [id] => 7239219 [patent_doc_number] => 20050140406 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-30 [patent_title] => 'Power-on reset device' [patent_app_type] => utility [patent_app_number] => 11/001779 [patent_app_country] => US [patent_app_date] => 2004-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3770 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20050140406.pdf [firstpage_image] =>[orig_patent_app_number] => 11001779 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/001779
Power-on reset device Nov 29, 2004 Abandoned
Array ( [id] => 5635394 [patent_doc_number] => 20060066367 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-30 [patent_title] => 'Method and system for providing a power-on reset pulse' [patent_app_type] => utility [patent_app_number] => 10/975103 [patent_app_country] => US [patent_app_date] => 2004-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2462 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20060066367.pdf [firstpage_image] =>[orig_patent_app_number] => 10975103 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/975103
Method and system for providing a power-on reset pulse Oct 27, 2004 Issued
Array ( [id] => 394488 [patent_doc_number] => 07298189 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-11-20 [patent_title] => 'Delay locked loop circuit' [patent_app_type] => utility [patent_app_number] => 10/965985 [patent_app_country] => US [patent_app_date] => 2004-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4558 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/298/07298189.pdf [firstpage_image] =>[orig_patent_app_number] => 10965985 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/965985
Delay locked loop circuit Oct 14, 2004 Issued
Array ( [id] => 6916037 [patent_doc_number] => 20050093598 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-05 [patent_title] => 'Delay-locked loop circuit' [patent_app_type] => utility [patent_app_number] => 10/965450 [patent_app_country] => US [patent_app_date] => 2004-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6058 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0093/20050093598.pdf [firstpage_image] =>[orig_patent_app_number] => 10965450 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/965450
Delay-locked loop circuit and method thereof for generating a clock signal Oct 13, 2004 Issued
Array ( [id] => 7081074 [patent_doc_number] => 20050046454 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-03 [patent_title] => 'Phase synchronization for wide area integrated circuits' [patent_app_type] => utility [patent_app_number] => 10/963698 [patent_app_country] => US [patent_app_date] => 2004-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3508 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20050046454.pdf [firstpage_image] =>[orig_patent_app_number] => 10963698 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/963698
Phase synchronization for wide area integrated circuits Oct 12, 2004 Issued
Array ( [id] => 7125557 [patent_doc_number] => 20050057301 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-17 [patent_title] => 'Semiconductor device and electronic apparatus capable of detecting open wire using weak current' [patent_app_type] => utility [patent_app_number] => 10/931445 [patent_app_country] => US [patent_app_date] => 2004-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3344 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0057/20050057301.pdf [firstpage_image] =>[orig_patent_app_number] => 10931445 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/931445
Semiconductor device capable of detecting an open bonding wire using weak current Aug 31, 2004 Issued
Array ( [id] => 830626 [patent_doc_number] => 07400182 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-15 [patent_title] => 'Clock generator with one pole and method for generating a clock' [patent_app_type] => utility [patent_app_number] => 10/915746 [patent_app_country] => US [patent_app_date] => 2004-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 3567 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/400/07400182.pdf [firstpage_image] =>[orig_patent_app_number] => 10915746 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/915746
Clock generator with one pole and method for generating a clock Aug 10, 2004 Issued
Array ( [id] => 7009787 [patent_doc_number] => 20050063503 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-24 [patent_title] => 'Digital clock modulator' [patent_app_type] => utility [patent_app_number] => 10/909939 [patent_app_country] => US [patent_app_date] => 2004-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4005 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0063/20050063503.pdf [firstpage_image] =>[orig_patent_app_number] => 10909939 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/909939
Digital clock modulator Aug 1, 2004 Issued
Array ( [id] => 331052 [patent_doc_number] => 07511551 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-31 [patent_title] => 'Voltage converter and method of performing the same' [patent_app_type] => utility [patent_app_number] => 10/844504 [patent_app_country] => US [patent_app_date] => 2004-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4951 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/511/07511551.pdf [firstpage_image] =>[orig_patent_app_number] => 10844504 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/844504
Voltage converter and method of performing the same May 12, 2004 Issued
Array ( [id] => 7067287 [patent_doc_number] => 20050242669 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-03 [patent_title] => 'Apparatus and method for shifting a signal from a first reference level to a second reference level' [patent_app_type] => utility [patent_app_number] => 10/836800 [patent_app_country] => US [patent_app_date] => 2004-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5545 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0242/20050242669.pdf [firstpage_image] =>[orig_patent_app_number] => 10836800 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/836800
Apparatus and method for shifting a signal from a first reference level to a second reference level Apr 29, 2004 Issued
Array ( [id] => 7335253 [patent_doc_number] => 20040189374 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-30 [patent_title] => 'Bias voltage generating circuit, amplifier circuit, and pipelined AD converter capable of switching current driving capabilities' [patent_app_type] => new [patent_app_number] => 10/808575 [patent_app_country] => US [patent_app_date] => 2004-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6152 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0189/20040189374.pdf [firstpage_image] =>[orig_patent_app_number] => 10808575 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/808575
Pipelined AD converter capable of switching current driving capabilities Mar 24, 2004 Issued
Array ( [id] => 7321577 [patent_doc_number] => 20040225930 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-11 [patent_title] => 'System and method for detecting an edge of a data signal' [patent_app_type] => new [patent_app_number] => 10/805979 [patent_app_country] => US [patent_app_date] => 2004-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3992 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0225/20040225930.pdf [firstpage_image] =>[orig_patent_app_number] => 10805979 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/805979
System and method for detecting an edge of a data signal Mar 21, 2004 Issued
Array ( [id] => 837577 [patent_doc_number] => 07394308 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-07-01 [patent_title] => 'Circuit and method for implementing a low supply voltage current reference' [patent_app_type] => utility [patent_app_number] => 10/796859 [patent_app_country] => US [patent_app_date] => 2004-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4569 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/394/07394308.pdf [firstpage_image] =>[orig_patent_app_number] => 10796859 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/796859
Circuit and method for implementing a low supply voltage current reference Mar 7, 2004 Issued
Array ( [id] => 7101915 [patent_doc_number] => 20050104641 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-19 [patent_title] => 'Schmitt trigger circuit realized with low-voltage devices for high-voltage signal application' [patent_app_type] => utility [patent_app_number] => 10/790842 [patent_app_country] => US [patent_app_date] => 2004-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2261 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0104/20050104641.pdf [firstpage_image] =>[orig_patent_app_number] => 10790842 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/790842
Schmitt trigger circuit realized with low-voltage devices for high-voltage signal application Mar 2, 2004 Abandoned
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