
Michael James Carey
Examiner (ID: 835)
| Most Active Art Unit | 3766 |
| Art Unit(s) | 3762, 4187, 3766, 3795, 3792 |
| Total Applications | 666 |
| Issued Applications | 554 |
| Pending Applications | 26 |
| Abandoned Applications | 95 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7133554
[patent_doc_number] => 20050179468
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-08-18
[patent_title] => 'Implementation of MOS capacitor in CT scanner data acquisition system'
[patent_app_type] => utility
[patent_app_number] => 10/779903
[patent_app_country] => US
[patent_app_date] => 2004-02-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 5154
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0179/20050179468.pdf
[firstpage_image] =>[orig_patent_app_number] => 10779903
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/779903 | Implementation of MOS capacitor in CT scanner data acquisition system | Feb 16, 2004 | Abandoned |
Array
(
[id] => 7319484
[patent_doc_number] => 20040135642
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-07-15
[patent_title] => 'Synchronizing circuit provided with hysteresis phase comparator'
[patent_app_type] => new
[patent_app_number] => 10/746454
[patent_app_country] => US
[patent_app_date] => 2003-12-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 6043
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0135/20040135642.pdf
[firstpage_image] =>[orig_patent_app_number] => 10746454
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/746454 | Synchronizing circuit provided with hysteresis phase comparator | Dec 23, 2003 | Issued |
Array
(
[id] => 594316
[patent_doc_number] => 07436230
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-10-14
[patent_title] => 'Delay locked loop with improved jitter and clock delay compensating method thereof'
[patent_app_type] => utility
[patent_app_number] => 10/746226
[patent_app_country] => US
[patent_app_date] => 2003-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 7551
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/436/07436230.pdf
[firstpage_image] =>[orig_patent_app_number] => 10746226
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/746226 | Delay locked loop with improved jitter and clock delay compensating method thereof | Dec 22, 2003 | Issued |
Array
(
[id] => 565929
[patent_doc_number] => 07471128
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-12-30
[patent_title] => 'Delay signal generator and recording pulse generator'
[patent_app_type] => utility
[patent_app_number] => 10/504607
[patent_app_country] => US
[patent_app_date] => 2003-11-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 6489
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 413
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/471/07471128.pdf
[firstpage_image] =>[orig_patent_app_number] => 10504607
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/504607 | Delay signal generator and recording pulse generator | Nov 6, 2003 | Issued |
Array
(
[id] => 412196
[patent_doc_number] => 07282981
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-10-16
[patent_title] => 'Level conversion circuit with improved margin of level shift operation and level shifting delays'
[patent_app_type] => utility
[patent_app_number] => 10/533807
[patent_app_country] => US
[patent_app_date] => 2003-11-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 38
[patent_figures_cnt] => 38
[patent_no_of_words] => 10925
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 12
[patent_words_short_claim] => 70
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/282/07282981.pdf
[firstpage_image] =>[orig_patent_app_number] => 10533807
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/533807 | Level conversion circuit with improved margin of level shift operation and level shifting delays | Nov 4, 2003 | Issued |
Array
(
[id] => 5653351
[patent_doc_number] => 20060139086
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-06-29
[patent_title] => 'Circuit arrangement for bridging high voltages using a switching signal'
[patent_app_type] => utility
[patent_app_number] => 10/528925
[patent_app_country] => US
[patent_app_date] => 2003-09-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4122
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0139/20060139086.pdf
[firstpage_image] =>[orig_patent_app_number] => 10528925
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/528925 | Circuit arrangement for bridging high voltages using a switching signal | Sep 24, 2003 | Abandoned |
Array
(
[id] => 5713618
[patent_doc_number] => 20060076981
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-04-13
[patent_title] => 'Phase detector with selection of differences between input signals'
[patent_app_type] => utility
[patent_app_number] => 10/523344
[patent_app_country] => US
[patent_app_date] => 2003-07-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2970
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0076/20060076981.pdf
[firstpage_image] =>[orig_patent_app_number] => 10523344
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/523344 | Phase detector with selection of differences between input signals | Jul 22, 2003 | Issued |
Array
(
[id] => 364031
[patent_doc_number] => 07482847
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-01-27
[patent_title] => 'Power-on reset circuit'
[patent_app_type] => utility
[patent_app_number] => 10/396811
[patent_app_country] => US
[patent_app_date] => 2003-03-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 3006
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 143
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/482/07482847.pdf
[firstpage_image] =>[orig_patent_app_number] => 10396811
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/396811 | Power-on reset circuit | Mar 25, 2003 | Issued |
Array
(
[id] => 7130589
[patent_doc_number] => 20040041618
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-03-04
[patent_title] => 'Method and system for reduction of off-current in field effect transistors'
[patent_app_type] => new
[patent_app_number] => 10/396312
[patent_app_country] => US
[patent_app_date] => 2003-03-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 4505
[patent_no_of_claims] => 84
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 44
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0041/20040041618.pdf
[firstpage_image] =>[orig_patent_app_number] => 10396312
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/396312 | Method and system for reduction of off-current in field effect transistors | Mar 25, 2003 | Issued |
Array
(
[id] => 7427109
[patent_doc_number] => 20040001551
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-01-01
[patent_title] => 'Data transmission circuit and method for reducing leakage current'
[patent_app_type] => new
[patent_app_number] => 10/390855
[patent_app_country] => US
[patent_app_date] => 2003-03-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 4616
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 57
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0001/20040001551.pdf
[firstpage_image] =>[orig_patent_app_number] => 10390855
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/390855 | Data transmission circuit and method for reducing leakage current | Mar 17, 2003 | Abandoned |
Array
(
[id] => 6657681
[patent_doc_number] => 20030133513
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-07-17
[patent_title] => 'Data interface circuit and data transmitting method'
[patent_app_type] => new
[patent_app_number] => 10/345579
[patent_app_country] => US
[patent_app_date] => 2003-01-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 6519
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0133/20030133513.pdf
[firstpage_image] =>[orig_patent_app_number] => 10345579
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/345579 | Data interface circuit and data transmitting method | Jan 15, 2003 | Issued |