Search

Michael Manh Trinh

Examiner (ID: 6883, Phone: (571)272-1847 , Office: P/2822 )

Most Active Art Unit
2822
Art Unit(s)
2813, 1763, 1104, 2822, 2898
Total Applications
2319
Issued Applications
1882
Pending Applications
50
Abandoned Applications
404

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17085444 [patent_doc_number] => 20210280451 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-09 [patent_title] => LOW TEMPERATURE STEAM FREE OXIDE GAPFILL [patent_app_type] => utility [patent_app_number] => 16/808688 [patent_app_country] => US [patent_app_date] => 2020-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6344 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16808688 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/808688
LOW TEMPERATURE STEAM FREE OXIDE GAPFILL Mar 3, 2020 Abandoned
Array ( [id] => 17424355 [patent_doc_number] => 11257817 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-22 [patent_title] => Integrated chip with improved latch-up immunity [patent_app_type] => utility [patent_app_number] => 16/808866 [patent_app_country] => US [patent_app_date] => 2020-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 58 [patent_no_of_words] => 19990 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 285 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16808866 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/808866
Integrated chip with improved latch-up immunity Mar 3, 2020 Issued
Array ( [id] => 17070846 [patent_doc_number] => 20210273063 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-02 [patent_title] => Wrap Around Contact Formation for VTFET [patent_app_type] => utility [patent_app_number] => 16/805744 [patent_app_country] => US [patent_app_date] => 2020-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8377 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16805744 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/805744
Wrap around contact formation for VTFET Feb 28, 2020 Issued
Array ( [id] => 17963643 [patent_doc_number] => 20220344224 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-27 [patent_title] => MOTHERBOARD AND MANUFACTURING METHOD FOR MOTHERBOARD [patent_app_type] => utility [patent_app_number] => 17/435098 [patent_app_country] => US [patent_app_date] => 2020-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10703 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17435098 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/435098
Motherboard and manufacturing method for motherboard Feb 26, 2020 Issued
Array ( [id] => 16746660 [patent_doc_number] => 10971665 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-06 [patent_title] => Photon extraction from nitride ultraviolet light-emitting devices [patent_app_type] => utility [patent_app_number] => 16/801358 [patent_app_country] => US [patent_app_date] => 2020-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 6295 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16801358 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/801358
Photon extraction from nitride ultraviolet light-emitting devices Feb 25, 2020 Issued
Array ( [id] => 17730878 [patent_doc_number] => 11387280 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-12 [patent_title] => Light-emitting device and electronic device [patent_app_type] => utility [patent_app_number] => 16/797167 [patent_app_country] => US [patent_app_date] => 2020-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 79 [patent_no_of_words] => 32757 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16797167 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/797167
Light-emitting device and electronic device Feb 20, 2020 Issued
Array ( [id] => 16226212 [patent_doc_number] => 20200251329 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-06 [patent_title] => METHOD OF PROCESSING SUBSTRATES AND SUBSTRATE PROCESSING APPARATUS [patent_app_type] => utility [patent_app_number] => 16/776774 [patent_app_country] => US [patent_app_date] => 2020-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5404 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16776774 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/776774
Method of processing substrates and substrate processing apparatus Jan 29, 2020 Issued
Array ( [id] => 17210678 [patent_doc_number] => 11171055 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-09 [patent_title] => UV laser slicing of b-Ga [patent_app_type] => utility [patent_app_number] => 16/776851 [patent_app_country] => US [patent_app_date] => 2020-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3163 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16776851 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/776851
UV laser slicing of b-Ga Jan 29, 2020 Issued
Array ( [id] => 17224857 [patent_doc_number] => 11177367 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-16 [patent_title] => Self-aligned bottom spacer EPI last flow for VTFET [patent_app_type] => utility [patent_app_number] => 16/743323 [patent_app_country] => US [patent_app_date] => 2020-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6105 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16743323 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/743323
Self-aligned bottom spacer EPI last flow for VTFET Jan 14, 2020 Issued
Array ( [id] => 17166248 [patent_doc_number] => 11152360 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-19 [patent_title] => Architecture of N and P transistors superposed with canal structure formed of nanowires [patent_app_type] => utility [patent_app_number] => 16/723285 [patent_app_country] => US [patent_app_date] => 2019-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 55 [patent_no_of_words] => 8906 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 302 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16723285 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/723285
Architecture of N and P transistors superposed with canal structure formed of nanowires Dec 19, 2019 Issued
Array ( [id] => 16479613 [patent_doc_number] => 10854567 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-01 [patent_title] => 3D packages and methods for forming the same [patent_app_type] => utility [patent_app_number] => 16/716811 [patent_app_country] => US [patent_app_date] => 2019-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 7841 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16716811 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/716811
3D packages and methods for forming the same Dec 16, 2019 Issued
Array ( [id] => 16233955 [patent_doc_number] => 10741518 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-11 [patent_title] => Method of fabricating semiconductor package [patent_app_type] => utility [patent_app_number] => 16/698117 [patent_app_country] => US [patent_app_date] => 2019-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 25 [patent_no_of_words] => 9694 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16698117 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/698117
Method of fabricating semiconductor package Nov 26, 2019 Issued
Array ( [id] => 16495804 [patent_doc_number] => 10861856 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-08 [patent_title] => Semiconductor device and method for fabricating the same [patent_app_type] => utility [patent_app_number] => 16/682652 [patent_app_country] => US [patent_app_date] => 2019-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 54 [patent_no_of_words] => 14724 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16682652 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/682652
Semiconductor device and method for fabricating the same Nov 12, 2019 Issued
Array ( [id] => 16773940 [patent_doc_number] => 10985061 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-20 [patent_title] => Methods for forming contact plugs with reduced corrosion [patent_app_type] => utility [patent_app_number] => 16/678410 [patent_app_country] => US [patent_app_date] => 2019-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5240 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16678410 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/678410
Methods for forming contact plugs with reduced corrosion Nov 7, 2019 Issued
Array ( [id] => 15597769 [patent_doc_number] => 20200075419 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-05 [patent_title] => Low-K Gate Spacer and Formation Thereof [patent_app_type] => utility [patent_app_number] => 16/674443 [patent_app_country] => US [patent_app_date] => 2019-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7377 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16674443 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/674443
Low-k gate spacer and formation thereof Nov 4, 2019 Issued
Array ( [id] => 15564239 [patent_doc_number] => 20200066531 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-27 [patent_title] => WELL AND PUNCH THROUGH STOPPER FORMATION USING CONFORMAL DOPING [patent_app_type] => utility [patent_app_number] => 16/671218 [patent_app_country] => US [patent_app_date] => 2019-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4227 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16671218 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/671218
Well and punch through stopper formation using conformal doping Oct 31, 2019 Issued
Array ( [id] => 15564645 [patent_doc_number] => 20200066734 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-27 [patent_title] => Flexible Merge Scheme for Source/Drain Epitaxy Regions [patent_app_type] => utility [patent_app_number] => 16/669736 [patent_app_country] => US [patent_app_date] => 2019-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5906 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16669736 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/669736
Flexible merge scheme for source/drain epitaxy regions Oct 30, 2019 Issued
Array ( [id] => 16495663 [patent_doc_number] => 10861711 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-12-08 [patent_title] => Method of manufacturing a semiconductor structure [patent_app_type] => utility [patent_app_number] => 16/660824 [patent_app_country] => US [patent_app_date] => 2019-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2624 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16660824 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/660824
Method of manufacturing a semiconductor structure Oct 22, 2019 Issued
Array ( [id] => 16098323 [patent_doc_number] => 20200203148 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-25 [patent_title] => METHOD FOR FABRICATING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/661234 [patent_app_country] => US [patent_app_date] => 2019-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9245 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16661234 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/661234
Method for fabricating semiconductor device Oct 22, 2019 Issued
Array ( [id] => 16617211 [patent_doc_number] => 20210035864 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-04 [patent_title] => Electronic Device Including a Polymer Support Layer and a Process of Forming the Same [patent_app_type] => utility [patent_app_number] => 16/661776 [patent_app_country] => US [patent_app_date] => 2019-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12279 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16661776 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/661776
Process of forming an electronic device including a polymer support layer Oct 22, 2019 Issued
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