Search

Michael Manh Trinh

Examiner (ID: 16750, Phone: (571)272-1847 , Office: P/2822 )

Most Active Art Unit
2822
Art Unit(s)
1104, 2898, 1763, 2822, 2813
Total Applications
2320
Issued Applications
1882
Pending Applications
52
Abandoned Applications
404

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18280036 [patent_doc_number] => 20230095508 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => SOURCE/DRAIN CONTACT POSITIONING UNDER POWER RAIL [patent_app_type] => utility [patent_app_number] => 17/491408 [patent_app_country] => US [patent_app_date] => 2021-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3805 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17491408 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/491408
Source/drain contact positioning under power rail Sep 29, 2021 Issued
Array ( [id] => 19016489 [patent_doc_number] => 11923434 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-05 [patent_title] => Self-aligned bottom spacer epi last flow for VTFET [patent_app_type] => utility [patent_app_number] => 17/481461 [patent_app_country] => US [patent_app_date] => 2021-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6105 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17481461 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/481461
Self-aligned bottom spacer epi last flow for VTFET Sep 21, 2021 Issued
Array ( [id] => 18548233 [patent_doc_number] => 11721592 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-08 [patent_title] => Method of making vertical semiconductor nanosheets with diffusion breaks [patent_app_type] => utility [patent_app_number] => 17/480318 [patent_app_country] => US [patent_app_date] => 2021-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 27 [patent_no_of_words] => 7550 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17480318 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/480318
Method of making vertical semiconductor nanosheets with diffusion breaks Sep 20, 2021 Issued
Array ( [id] => 19842803 [patent_doc_number] => 12255204 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-18 [patent_title] => Vertical FET replacement gate formation with variable fin pitch [patent_app_type] => utility [patent_app_number] => 17/479145 [patent_app_country] => US [patent_app_date] => 2021-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6243 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17479145 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/479145
Vertical FET replacement gate formation with variable fin pitch Sep 19, 2021 Issued
Array ( [id] => 19796359 [patent_doc_number] => 12237330 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-25 [patent_title] => Architecture with stacked N and P transistors with a channel structure formed of nanowires [patent_app_type] => utility [patent_app_number] => 17/461428 [patent_app_country] => US [patent_app_date] => 2021-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 55 [patent_no_of_words] => 10140 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 520 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17461428 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/461428
Architecture with stacked N and P transistors with a channel structure formed of nanowires Aug 29, 2021 Issued
Array ( [id] => 18209037 [patent_doc_number] => 20230055297 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-23 [patent_title] => SELF-ALIGNED BLOCK FOR VERTICAL FETS [patent_app_type] => utility [patent_app_number] => 17/404014 [patent_app_country] => US [patent_app_date] => 2021-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9047 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17404014 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/404014
Self-aligned block for vertical FETs Aug 16, 2021 Issued
Array ( [id] => 18967696 [patent_doc_number] => 11901480 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-13 [patent_title] => Method of manufacturing a light-emitting device [patent_app_type] => utility [patent_app_number] => 17/397388 [patent_app_country] => US [patent_app_date] => 2021-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 19 [patent_no_of_words] => 6619 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17397388 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/397388
Method of manufacturing a light-emitting device Aug 8, 2021 Issued
Array ( [id] => 19428334 [patent_doc_number] => 12087770 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-10 [patent_title] => Complementary field effect transistor devices [patent_app_type] => utility [patent_app_number] => 17/394701 [patent_app_country] => US [patent_app_date] => 2021-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7181 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17394701 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/394701
Complementary field effect transistor devices Aug 4, 2021 Issued
Array ( [id] => 18179983 [patent_doc_number] => 20230040712 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-09 [patent_title] => STACKED COMPLEMENTARY FIELD EFFECT TRANSISTORS [patent_app_type] => utility [patent_app_number] => 17/392691 [patent_app_country] => US [patent_app_date] => 2021-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7439 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17392691 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/392691
Stacked complementary field effect transistors Aug 2, 2021 Issued
Array ( [id] => 17232287 [patent_doc_number] => 20210358844 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-18 [patent_title] => INTEGRATED CIRCUIT WITH GUARD RING [patent_app_type] => utility [patent_app_number] => 17/389795 [patent_app_country] => US [patent_app_date] => 2021-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4030 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17389795 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/389795
Integrated circuit with guard ring Jul 29, 2021 Issued
Array ( [id] => 17203714 [patent_doc_number] => 20210343809 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-04 [patent_title] => ORGANIC LIGHT-EMITTING DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 17/379913 [patent_app_country] => US [patent_app_date] => 2021-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10320 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17379913 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/379913
Organic light-emitting display device Jul 18, 2021 Issued
Array ( [id] => 17203642 [patent_doc_number] => 20210343737 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-04 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/376856 [patent_app_country] => US [patent_app_date] => 2021-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10489 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17376856 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/376856
Semiconductor memory device Jul 14, 2021 Issued
Array ( [id] => 18394811 [patent_doc_number] => 20230163032 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-25 [patent_title] => FORMING A WRAP-AROUND CONTACT TO CONNECT A SOURCE OR DRAIN EPITAXIAL GROWTH OF A COMPLIMENTARY FIELD EFFECT TRANSISTOR (CFET) TO A BURIED POWER RAIL (BPR) OF THE CFET [patent_app_type] => utility [patent_app_number] => 17/372249 [patent_app_country] => US [patent_app_date] => 2021-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6596 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17372249 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/372249
Forming a wrap-around contact to connect a source or drain epitaxial growth of a complimentary field effect transistor (CFET) to a buried power rail (BPR) of the CFET Jul 8, 2021 Issued
Array ( [id] => 18593336 [patent_doc_number] => 11742247 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-29 [patent_title] => Epitaxial growth of source and drain materials in a complementary field effect transistor (CFET) [patent_app_type] => utility [patent_app_number] => 17/372231 [patent_app_country] => US [patent_app_date] => 2021-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 6546 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17372231 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/372231
Epitaxial growth of source and drain materials in a complementary field effect transistor (CFET) Jul 8, 2021 Issued
Array ( [id] => 19341500 [patent_doc_number] => 12051697 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-30 [patent_title] => Integrated circuit devices including stacked gate structures with different dimensions [patent_app_type] => utility [patent_app_number] => 17/361381 [patent_app_country] => US [patent_app_date] => 2021-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 37 [patent_no_of_words] => 6882 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17361381 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/361381
Integrated circuit devices including stacked gate structures with different dimensions Jun 28, 2021 Issued
Array ( [id] => 17145311 [patent_doc_number] => 20210313324 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-07 [patent_title] => Method for Forming Source/Drain Contacts [patent_app_type] => utility [patent_app_number] => 17/347066 [patent_app_country] => US [patent_app_date] => 2021-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9467 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17347066 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/347066
Method for forming source/drain contacts Jun 13, 2021 Issued
Array ( [id] => 18507539 [patent_doc_number] => 11705366 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-18 [patent_title] => Methods for controllable metal and barrier-liner recess [patent_app_type] => utility [patent_app_number] => 17/345683 [patent_app_country] => US [patent_app_date] => 2021-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 17 [patent_no_of_words] => 5467 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17345683 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/345683
Methods for controllable metal and barrier-liner recess Jun 10, 2021 Issued
Array ( [id] => 17509242 [patent_doc_number] => 20220102345 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => PLURALITY OF 3D VERTICAL CMOS DEVICES FOR HIGH PERFORMANCE LOGIC [patent_app_type] => utility [patent_app_number] => 17/335563 [patent_app_country] => US [patent_app_date] => 2021-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4695 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17335563 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/335563
PLURALITY OF 3D VERTICAL CMOS DEVICES FOR HIGH PERFORMANCE LOGIC May 31, 2021 Abandoned
Array ( [id] => 19567883 [patent_doc_number] => 12142664 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-12 [patent_title] => Reducing metal gate overhang by forming a top-wide bottom-narrow dummy gate electrode [patent_app_type] => utility [patent_app_number] => 17/323557 [patent_app_country] => US [patent_app_date] => 2021-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6066 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17323557 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/323557
Reducing metal gate overhang by forming a top-wide bottom-narrow dummy gate electrode May 17, 2021 Issued
Array ( [id] => 17232262 [patent_doc_number] => 20210358819 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-18 [patent_title] => USING A TRAINED NEURAL NETWORK FOR USE IN IN-SITU MONITORING DURING POLISHING AND POLISHING SYSTEM [patent_app_type] => utility [patent_app_number] => 17/317501 [patent_app_country] => US [patent_app_date] => 2021-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7786 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17317501 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/317501
Using a trained neural network for use in in-situ monitoring during polishing and polishing system May 10, 2021 Issued
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