Michael P Barker
Examiner (ID: 12455, Phone: (571)272-0303 , Office: P/1626 )
Most Active Art Unit | 1626 |
Art Unit(s) | OPQA, 1626, 1655 |
Total Applications | 1330 |
Issued Applications | 1012 |
Pending Applications | 61 |
Abandoned Applications | 257 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 3966681
[patent_doc_number] => 05956566
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-09-21
[patent_title] => 'Method and test site to monitor alignment shift and buried contact trench formation'
[patent_app_type] => 1
[patent_app_number] => 9/213454
[patent_app_country] => US
[patent_app_date] => 1998-12-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 10
[patent_no_of_words] => 3454
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 282
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/956/05956566.pdf
[firstpage_image] =>[orig_patent_app_number] => 213454
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/213454 | Method and test site to monitor alignment shift and buried contact trench formation | Dec 16, 1998 | Issued |
Array
(
[id] => 4084886
[patent_doc_number] => 06025250
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-02-15
[patent_title] => 'Methods including wafer grooves for reducing semiconductor wafer warping and related structure'
[patent_app_type] => 1
[patent_app_number] => 9/190044
[patent_app_country] => US
[patent_app_date] => 1998-11-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 2344
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/025/06025250.pdf
[firstpage_image] =>[orig_patent_app_number] => 190044
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/190044 | Methods including wafer grooves for reducing semiconductor wafer warping and related structure | Nov 9, 1998 | Issued |
Array
(
[id] => 4237572
[patent_doc_number] => 06090703
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-07-18
[patent_title] => 'Method of forming an integrated circuit having conductors of enhanced cross-sectional area with etch stop barrier layer'
[patent_app_type] => 1
[patent_app_number] => 9/165765
[patent_app_country] => US
[patent_app_date] => 1998-10-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 16
[patent_no_of_words] => 3484
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 186
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/090/06090703.pdf
[firstpage_image] =>[orig_patent_app_number] => 165765
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/165765 | Method of forming an integrated circuit having conductors of enhanced cross-sectional area with etch stop barrier layer | Oct 1, 1998 | Issued |
Array
(
[id] => 3911438
[patent_doc_number] => 06001733
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-12-14
[patent_title] => 'Method of forming a dual damascene with dummy metal lines'
[patent_app_type] => 1
[patent_app_number] => 9/164856
[patent_app_country] => US
[patent_app_date] => 1998-10-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 15
[patent_no_of_words] => 3582
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 336
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/001/06001733.pdf
[firstpage_image] =>[orig_patent_app_number] => 164856
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/164856 | Method of forming a dual damascene with dummy metal lines | Sep 30, 1998 | Issued |
Array
(
[id] => 4085363
[patent_doc_number] => 06017782
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-01-25
[patent_title] => 'Thin film transistor and method of forming thin film transistors'
[patent_app_type] => 1
[patent_app_number] => 9/124939
[patent_app_country] => US
[patent_app_date] => 1998-07-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 3744
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/017/06017782.pdf
[firstpage_image] =>[orig_patent_app_number] => 124939
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/124939 | Thin film transistor and method of forming thin film transistors | Jul 28, 1998 | Issued |
Array
(
[id] => 3968385
[patent_doc_number] => 05904489
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-05-18
[patent_title] => 'Topside analysis of a multi-layer integrated circuit die mounted in a flip-chip package'
[patent_app_type] => 1
[patent_app_number] => 9/122835
[patent_app_country] => US
[patent_app_date] => 1998-07-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 5
[patent_no_of_words] => 1140
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/904/05904489.pdf
[firstpage_image] =>[orig_patent_app_number] => 122835
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/122835 | Topside analysis of a multi-layer integrated circuit die mounted in a flip-chip package | Jul 26, 1998 | Issued |
Array
(
[id] => 4106247
[patent_doc_number] => 06022754
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-02-08
[patent_title] => 'Electronic device and method for forming a membrane for an electronic device'
[patent_app_type] => 1
[patent_app_number] => 9/120755
[patent_app_country] => US
[patent_app_date] => 1998-07-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 10
[patent_no_of_words] => 2827
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/022/06022754.pdf
[firstpage_image] =>[orig_patent_app_number] => 120755
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/120755 | Electronic device and method for forming a membrane for an electronic device | Jul 21, 1998 | Issued |
Array
(
[id] => 3956847
[patent_doc_number] => 05930598
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-07-27
[patent_title] => 'Microelectronic assembly including a decomposable encapsulant, and method for forming and reworking same'
[patent_app_type] => 1
[patent_app_number] => 9/120164
[patent_app_country] => US
[patent_app_date] => 1998-07-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 3
[patent_no_of_words] => 2687
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 71
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/930/05930598.pdf
[firstpage_image] =>[orig_patent_app_number] => 120164
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/120164 | Microelectronic assembly including a decomposable encapsulant, and method for forming and reworking same | Jul 20, 1998 | Issued |
Array
(
[id] => 3911465
[patent_doc_number] => 06001735
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-12-14
[patent_title] => 'Dual damascene technique'
[patent_app_type] => 1
[patent_app_number] => 9/110545
[patent_app_country] => US
[patent_app_date] => 1998-07-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 6
[patent_no_of_words] => 1515
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 153
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/001/06001735.pdf
[firstpage_image] =>[orig_patent_app_number] => 110545
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/110545 | Dual damascene technique | Jul 5, 1998 | Issued |
Array
(
[id] => 4084381
[patent_doc_number] => 06025216
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-02-15
[patent_title] => 'TET-LCD method for manufacturing the same'
[patent_app_type] => 1
[patent_app_number] => 9/105044
[patent_app_country] => US
[patent_app_date] => 1998-06-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 16
[patent_no_of_words] => 3046
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 174
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/025/06025216.pdf
[firstpage_image] =>[orig_patent_app_number] => 105044
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/105044 | TET-LCD method for manufacturing the same | Jun 25, 1998 | Issued |
Array
(
[id] => 4050815
[patent_doc_number] => 05943597
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-08-24
[patent_title] => 'Bumped semiconductor device having a trench for stress relief'
[patent_app_type] => 1
[patent_app_number] => 9/094974
[patent_app_country] => US
[patent_app_date] => 1998-06-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 1796
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 64
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/943/05943597.pdf
[firstpage_image] =>[orig_patent_app_number] => 094974
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/094974 | Bumped semiconductor device having a trench for stress relief | Jun 14, 1998 | Issued |
Array
(
[id] => 4063595
[patent_doc_number] => 06008070
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-12-28
[patent_title] => 'Wafer level fabrication and assembly of chip scale packages'
[patent_app_type] => 1
[patent_app_number] => 9/082745
[patent_app_country] => US
[patent_app_date] => 1998-05-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 11
[patent_no_of_words] => 3309
[patent_no_of_claims] => 60
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 157
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/008/06008070.pdf
[firstpage_image] =>[orig_patent_app_number] => 082745
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/082745 | Wafer level fabrication and assembly of chip scale packages | May 20, 1998 | Issued |
Array
(
[id] => 3943866
[patent_doc_number] => 05998240
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-12-07
[patent_title] => 'Method of extracting heat from a semiconductor body and forming microchannels therein'
[patent_app_type] => 1
[patent_app_number] => 9/071776
[patent_app_country] => US
[patent_app_date] => 1998-05-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 25
[patent_no_of_words] => 4108
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/998/05998240.pdf
[firstpage_image] =>[orig_patent_app_number] => 071776
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/071776 | Method of extracting heat from a semiconductor body and forming microchannels therein | May 3, 1998 | Issued |
Array
(
[id] => 4058575
[patent_doc_number] => 05913108
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-06-15
[patent_title] => 'Laser diode packaging'
[patent_app_type] => 1
[patent_app_number] => 9/070859
[patent_app_country] => US
[patent_app_date] => 1998-04-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 15
[patent_no_of_words] => 8405
[patent_no_of_claims] => 40
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/913/05913108.pdf
[firstpage_image] =>[orig_patent_app_number] => 070859
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/070859 | Laser diode packaging | Apr 29, 1998 | Issued |
Array
(
[id] => 3976633
[patent_doc_number] => 05937320
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-08-10
[patent_title] => 'Barrier layers for electroplated SnPb eutectic solder joints'
[patent_app_type] => 1
[patent_app_number] => 9/057205
[patent_app_country] => US
[patent_app_date] => 1998-04-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 10
[patent_no_of_words] => 4208
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 158
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/937/05937320.pdf
[firstpage_image] =>[orig_patent_app_number] => 057205
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/057205 | Barrier layers for electroplated SnPb eutectic solder joints | Apr 7, 1998 | Issued |
Array
(
[id] => 4058546
[patent_doc_number] => 05913106
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-06-15
[patent_title] => 'Method for testing junction leakage of salicided devices fabricated using shallow trench and refill techniques'
[patent_app_type] => 1
[patent_app_number] => 9/046974
[patent_app_country] => US
[patent_app_date] => 1998-03-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 10
[patent_no_of_words] => 3365
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/913/05913106.pdf
[firstpage_image] =>[orig_patent_app_number] => 046974
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/046974 | Method for testing junction leakage of salicided devices fabricated using shallow trench and refill techniques | Mar 23, 1998 | Issued |
Array
(
[id] => 4113709
[patent_doc_number] => 06046072
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-04-04
[patent_title] => 'Process for fabricating a crack resistant resin encapsulated semiconductor chip package'
[patent_app_type] => 1
[patent_app_number] => 9/044575
[patent_app_country] => US
[patent_app_date] => 1998-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 3
[patent_no_of_words] => 10977
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 201
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/046/06046072.pdf
[firstpage_image] =>[orig_patent_app_number] => 044575
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/044575 | Process for fabricating a crack resistant resin encapsulated semiconductor chip package | Mar 18, 1998 | Issued |
Array
(
[id] => 3999217
[patent_doc_number] => 05950067
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-09-07
[patent_title] => 'Method of fabricating a thermoelectric module'
[patent_app_type] => 1
[patent_app_number] => 8/973095
[patent_app_country] => US
[patent_app_date] => 1998-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 42
[patent_no_of_words] => 7540
[patent_no_of_claims] => 37
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 294
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/950/05950067.pdf
[firstpage_image] =>[orig_patent_app_number] => 973095
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/973095 | Method of fabricating a thermoelectric module | Mar 18, 1998 | Issued |
09/042875 | METHOD AND STRUCTURE FOR CONSTRAINING THE FLOW OF ENCAPSULANT APPLIED TO AN I/C CHIP ON A SUBSTRATE | Mar 16, 1998 | Issued |
Array
(
[id] => 4017894
[patent_doc_number] => 05902120
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-05-11
[patent_title] => 'Process for producing spatially patterned components'
[patent_app_type] => 1
[patent_app_number] => 9/041805
[patent_app_country] => US
[patent_app_date] => 1998-03-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 5
[patent_no_of_words] => 2132
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 158
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/902/05902120.pdf
[firstpage_image] =>[orig_patent_app_number] => 041805
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/041805 | Process for producing spatially patterned components | Mar 12, 1998 | Issued |