Search

Michael P Barker

Examiner (ID: 12455, Phone: (571)272-0303 , Office: P/1626 )

Most Active Art Unit
1626
Art Unit(s)
OPQA, 1626, 1655
Total Applications
1330
Issued Applications
1012
Pending Applications
61
Abandoned Applications
257

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4237367 [patent_doc_number] => 06090689 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-18 [patent_title] => 'Method of forming buried oxide layers in silicon' [patent_app_type] => 1 [patent_app_number] => 9/034445 [patent_app_country] => US [patent_app_date] => 1998-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 4064 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/090/06090689.pdf [firstpage_image] =>[orig_patent_app_number] => 034445 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/034445
Method of forming buried oxide layers in silicon Mar 3, 1998 Issued
Array ( [id] => 3980360 [patent_doc_number] => 05910015 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-08 [patent_title] => 'Thin film transistor and manufacturing method of the thin film transistor' [patent_app_type] => 1 [patent_app_number] => 9/025616 [patent_app_country] => US [patent_app_date] => 1998-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2388 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/910/05910015.pdf [firstpage_image] =>[orig_patent_app_number] => 025616 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/025616
Thin film transistor and manufacturing method of the thin film transistor Feb 17, 1998 Issued
Array ( [id] => 3941358 [patent_doc_number] => 05989945 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-23 [patent_title] => 'Thin film device provided with coating film, liquid crystal panel and electronic device, and method for making the thin film device' [patent_app_type] => 1 [patent_app_number] => 8/983036 [patent_app_country] => US [patent_app_date] => 1998-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 73 [patent_no_of_words] => 20721 [patent_no_of_claims] => 57 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/989/05989945.pdf [firstpage_image] =>[orig_patent_app_number] => 983036 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/983036
Thin film device provided with coating film, liquid crystal panel and electronic device, and method for making the thin film device Feb 12, 1998 Issued
Array ( [id] => 4016036 [patent_doc_number] => 05923954 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-13 [patent_title] => 'Ball grid array package and fabrication method therefor' [patent_app_type] => 1 [patent_app_number] => 9/023286 [patent_app_country] => US [patent_app_date] => 1998-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 1621 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/923/05923954.pdf [firstpage_image] =>[orig_patent_app_number] => 023286 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/023286
Ball grid array package and fabrication method therefor Feb 12, 1998 Issued
Array ( [id] => 4142144 [patent_doc_number] => 06030900 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-29 [patent_title] => 'Process for generating a space in a structure' [patent_app_type] => 1 [patent_app_number] => 9/011375 [patent_app_country] => US [patent_app_date] => 1998-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2054 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/030/06030900.pdf [firstpage_image] =>[orig_patent_app_number] => 011375 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/011375
Process for generating a space in a structure Feb 3, 1998 Issued
Array ( [id] => 4029987 [patent_doc_number] => 05994221 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'Method of fabricating aluminum-indium (or thallium) vias for ULSI metallization and interconnects' [patent_app_type] => 1 [patent_app_number] => 9/016475 [patent_app_country] => US [patent_app_date] => 1998-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2956 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/994/05994221.pdf [firstpage_image] =>[orig_patent_app_number] => 016475 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/016475
Method of fabricating aluminum-indium (or thallium) vias for ULSI metallization and interconnects Jan 29, 1998 Issued
Array ( [id] => 4136733 [patent_doc_number] => 06015750 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-18 [patent_title] => 'Method for improving visibility of alignment target in semiconductor processing' [patent_app_type] => 1 [patent_app_number] => 9/007694 [patent_app_country] => US [patent_app_date] => 1998-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 2686 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/015/06015750.pdf [firstpage_image] =>[orig_patent_app_number] => 007694 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/007694
Method for improving visibility of alignment target in semiconductor processing Jan 14, 1998 Issued
Array ( [id] => 4180994 [patent_doc_number] => 06020222 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-01 [patent_title] => 'Silicon oxide insulator (SOI) semiconductor having selectively linked body' [patent_app_type] => 1 [patent_app_number] => 8/991808 [patent_app_country] => US [patent_app_date] => 1997-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 5944 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/020/06020222.pdf [firstpage_image] =>[orig_patent_app_number] => 991808 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/991808
Silicon oxide insulator (SOI) semiconductor having selectively linked body Dec 15, 1997 Issued
Array ( [id] => 3993921 [patent_doc_number] => 05985732 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'Method of forming integrated stacked capacitors with rounded corners' [patent_app_type] => 1 [patent_app_number] => 8/974204 [patent_app_country] => US [patent_app_date] => 1997-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4774 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/985/05985732.pdf [firstpage_image] =>[orig_patent_app_number] => 974204 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/974204
Method of forming integrated stacked capacitors with rounded corners Nov 18, 1997 Issued
Array ( [id] => 4064055 [patent_doc_number] => 06008101 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-28 [patent_title] => 'Laser processing method of semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/968480 [patent_app_country] => US [patent_app_date] => 1997-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 7256 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/008/06008101.pdf [firstpage_image] =>[orig_patent_app_number] => 968480 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/968480
Laser processing method of semiconductor device Nov 11, 1997 Issued
Array ( [id] => 4016133 [patent_doc_number] => 05923961 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-13 [patent_title] => 'Method of making an active matrix type display' [patent_app_type] => 1 [patent_app_number] => 8/968025 [patent_app_country] => US [patent_app_date] => 1997-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 29 [patent_no_of_words] => 7241 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/923/05923961.pdf [firstpage_image] =>[orig_patent_app_number] => 968025 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/968025
Method of making an active matrix type display Nov 11, 1997 Issued
Array ( [id] => 4012600 [patent_doc_number] => 05880016 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-09 [patent_title] => 'Method for adjusting the circuit characteristic of a circuit body by cutting wires external to the circuit body' [patent_app_type] => 1 [patent_app_number] => 8/961064 [patent_app_country] => US [patent_app_date] => 1997-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1812 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/880/05880016.pdf [firstpage_image] =>[orig_patent_app_number] => 961064 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/961064
Method for adjusting the circuit characteristic of a circuit body by cutting wires external to the circuit body Oct 29, 1997 Issued
Array ( [id] => 3975934 [patent_doc_number] => 05937275 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-10 [patent_title] => 'Method of producing acceleration sensors' [patent_app_type] => 1 [patent_app_number] => 8/809945 [patent_app_country] => US [patent_app_date] => 1997-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 2423 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/937/05937275.pdf [firstpage_image] =>[orig_patent_app_number] => 809945 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/809945
Method of producing acceleration sensors Oct 26, 1997 Issued
Array ( [id] => 3956801 [patent_doc_number] => 05930595 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'Isolation process for surface micromachined sensors and actuators' [patent_app_type] => 1 [patent_app_number] => 8/950776 [patent_app_country] => US [patent_app_date] => 1997-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 2566 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/930/05930595.pdf [firstpage_image] =>[orig_patent_app_number] => 950776 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/950776
Isolation process for surface micromachined sensors and actuators Oct 14, 1997 Issued
Array ( [id] => 3943457 [patent_doc_number] => 05976926 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Static memory cell and method of manufacturing a static memory cell' [patent_app_type] => 1 [patent_app_number] => 8/948889 [patent_app_country] => US [patent_app_date] => 1997-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 20 [patent_no_of_words] => 9084 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/976/05976926.pdf [firstpage_image] =>[orig_patent_app_number] => 948889 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/948889
Static memory cell and method of manufacturing a static memory cell Oct 9, 1997 Issued
Array ( [id] => 3885780 [patent_doc_number] => 05893725 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-13 [patent_title] => 'C4 substrate contact pad which has a layer of NI-B plating' [patent_app_type] => 1 [patent_app_number] => 8/946418 [patent_app_country] => US [patent_app_date] => 1997-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 11 [patent_no_of_words] => 1472 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/893/05893725.pdf [firstpage_image] =>[orig_patent_app_number] => 946418 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/946418
C4 substrate contact pad which has a layer of NI-B plating Oct 6, 1997 Issued
Array ( [id] => 4070789 [patent_doc_number] => 05970367 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-19 [patent_title] => 'Double damascene pattering of silcon-on-insulator transistors' [patent_app_type] => 1 [patent_app_number] => 8/942323 [patent_app_country] => US [patent_app_date] => 1997-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 1592 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 318 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/970/05970367.pdf [firstpage_image] =>[orig_patent_app_number] => 942323 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/942323
Double damascene pattering of silcon-on-insulator transistors Sep 30, 1997 Issued
Array ( [id] => 3968343 [patent_doc_number] => 05904486 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-18 [patent_title] => 'Method for performing a circuit edit through the back side of an integrated circuit die' [patent_app_type] => 1 [patent_app_number] => 8/940624 [patent_app_country] => US [patent_app_date] => 1997-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6079 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/904/05904486.pdf [firstpage_image] =>[orig_patent_app_number] => 940624 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/940624
Method for performing a circuit edit through the back side of an integrated circuit die Sep 29, 1997 Issued
Array ( [id] => 4070804 [patent_doc_number] => 05970368 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-19 [patent_title] => 'Method for manufacturing polycrystal semiconductor film' [patent_app_type] => 1 [patent_app_number] => 8/939660 [patent_app_country] => US [patent_app_date] => 1997-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 29 [patent_no_of_words] => 12382 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/970/05970368.pdf [firstpage_image] =>[orig_patent_app_number] => 939660 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/939660
Method for manufacturing polycrystal semiconductor film Sep 28, 1997 Issued
Array ( [id] => 3911076 [patent_doc_number] => 06001714 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-14 [patent_title] => 'Method and apparatus for manufacturing polysilicon thin film transistor' [patent_app_type] => 1 [patent_app_number] => 8/938314 [patent_app_country] => US [patent_app_date] => 1997-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 36 [patent_no_of_words] => 7901 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/001/06001714.pdf [firstpage_image] =>[orig_patent_app_number] => 938314 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/938314
Method and apparatus for manufacturing polysilicon thin film transistor Sep 25, 1997 Issued
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