Michael P Barker
Examiner (ID: 12455, Phone: (571)272-0303 , Office: P/1626 )
Most Active Art Unit | 1626 |
Art Unit(s) | OPQA, 1626, 1655 |
Total Applications | 1330 |
Issued Applications | 1012 |
Pending Applications | 61 |
Abandoned Applications | 257 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 4029266
[patent_doc_number] => 05994173
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-30
[patent_title] => 'Thin film transistor matrix device and method for fabricating the same'
[patent_app_type] => 1
[patent_app_number] => 8/941224
[patent_app_country] => US
[patent_app_date] => 1997-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 60
[patent_figures_cnt] => 146
[patent_no_of_words] => 29560
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 157
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/994/05994173.pdf
[firstpage_image] =>[orig_patent_app_number] => 941224
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/941224 | Thin film transistor matrix device and method for fabricating the same | Sep 25, 1997 | Issued |
Array
(
[id] => 4108008
[patent_doc_number] => 06057235
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-05-02
[patent_title] => 'Method for reducing surface charge on semiconducter wafers to prevent arcing during plasma deposition'
[patent_app_type] => 1
[patent_app_number] => 8/929476
[patent_app_country] => US
[patent_app_date] => 1997-09-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 3262
[patent_no_of_claims] => 17
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[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/057/06057235.pdf
[firstpage_image] =>[orig_patent_app_number] => 929476
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/929476 | Method for reducing surface charge on semiconducter wafers to prevent arcing during plasma deposition | Sep 14, 1997 | Issued |
Array
(
[id] => 4064642
[patent_doc_number] => 06008143
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-12-28
[patent_title] => 'Metal organic chemical vapor deposition apparatus and deposition method'
[patent_app_type] => 1
[patent_app_number] => 8/921560
[patent_app_country] => US
[patent_app_date] => 1997-09-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 1812
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 147
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/008/06008143.pdf
[firstpage_image] =>[orig_patent_app_number] => 921560
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/921560 | Metal organic chemical vapor deposition apparatus and deposition method | Sep 1, 1997 | Issued |
Array
(
[id] => 3968510
[patent_doc_number] => 05904497
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-05-18
[patent_title] => 'Method and apparatus for semiconductor assembly which includes testing of chips and replacement of bad chips prior to final assembly'
[patent_app_type] => 1
[patent_app_number] => 8/916812
[patent_app_country] => US
[patent_app_date] => 1997-08-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 12
[patent_no_of_words] => 3636
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 57
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/904/05904497.pdf
[firstpage_image] =>[orig_patent_app_number] => 916812
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/916812 | Method and apparatus for semiconductor assembly which includes testing of chips and replacement of bad chips prior to final assembly | Aug 21, 1997 | Issued |
Array
(
[id] => 4107106
[patent_doc_number] => 06022813
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-02-08
[patent_title] => 'Method and apparatus for manufacturing semiconductor devices'
[patent_app_type] => 1
[patent_app_number] => 8/916376
[patent_app_country] => US
[patent_app_date] => 1997-08-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 16
[patent_no_of_words] => 4156
[patent_no_of_claims] => 27
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/022/06022813.pdf
[firstpage_image] =>[orig_patent_app_number] => 916376
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/916376 | Method and apparatus for manufacturing semiconductor devices | Aug 21, 1997 | Issued |
Array
(
[id] => 4136374
[patent_doc_number] => 06015725
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-01-18
[patent_title] => 'Vertical field effect transistor and manufacturing method thereof'
[patent_app_type] => 1
[patent_app_number] => 8/914096
[patent_app_country] => US
[patent_app_date] => 1997-08-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
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[patent_no_of_words] => 4281
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[patent_words_short_claim] => 181
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/015/06015725.pdf
[firstpage_image] =>[orig_patent_app_number] => 914096
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/914096 | Vertical field effect transistor and manufacturing method thereof | Aug 18, 1997 | Issued |
Array
(
[id] => 4098331
[patent_doc_number] => 06048803
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-04-11
[patent_title] => 'Method of fabricating a semiconductor device having fluorine bearing oxide between conductive lines'
[patent_app_type] => 1
[patent_app_number] => 8/914658
[patent_app_country] => US
[patent_app_date] => 1997-08-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 6
[patent_no_of_words] => 2148
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/048/06048803.pdf
[firstpage_image] =>[orig_patent_app_number] => 914658
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/914658 | Method of fabricating a semiconductor device having fluorine bearing oxide between conductive lines | Aug 18, 1997 | Issued |
Array
(
[id] => 4219325
[patent_doc_number] => 06040249
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-03-21
[patent_title] => 'Method of improving diffusion barrier properties of gate oxides by applying ions or free radicals of nitrogen in low energy'
[patent_app_type] => 1
[patent_app_number] => 8/907668
[patent_app_country] => US
[patent_app_date] => 1997-08-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 1287
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/040/06040249.pdf
[firstpage_image] =>[orig_patent_app_number] => 907668
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/907668 | Method of improving diffusion barrier properties of gate oxides by applying ions or free radicals of nitrogen in low energy | Aug 7, 1997 | Issued |
Array
(
[id] => 4206254
[patent_doc_number] => 06027950
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-02-22
[patent_title] => 'Method for achieving accurate SOG etchback selectivity'
[patent_app_type] => 1
[patent_app_number] => 8/906482
[patent_app_country] => US
[patent_app_date] => 1997-08-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 3605
[patent_no_of_claims] => 3
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/027/06027950.pdf
[firstpage_image] =>[orig_patent_app_number] => 906482
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/906482 | Method for achieving accurate SOG etchback selectivity | Aug 4, 1997 | Issued |
Array
(
[id] => 3942039
[patent_doc_number] => 05946562
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-08-31
[patent_title] => 'Polysilicon thin film transistors with laser-induced solid phase crystallized polysilicon channel'
[patent_app_type] => 1
[patent_app_number] => 8/903639
[patent_app_country] => US
[patent_app_date] => 1997-07-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 25
[patent_no_of_words] => 5104
[patent_no_of_claims] => 18
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/946/05946562.pdf
[firstpage_image] =>[orig_patent_app_number] => 903639
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/903639 | Polysilicon thin film transistors with laser-induced solid phase crystallized polysilicon channel | Jul 30, 1997 | Issued |
Array
(
[id] => 4038804
[patent_doc_number] => 05926702
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-07-20
[patent_title] => 'Method of fabricating TFT array substrate'
[patent_app_type] => 1
[patent_app_number] => 8/901676
[patent_app_country] => US
[patent_app_date] => 1997-07-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 21
[patent_no_of_words] => 5906
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/926/05926702.pdf
[firstpage_image] =>[orig_patent_app_number] => 901676
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/901676 | Method of fabricating TFT array substrate | Jul 27, 1997 | Issued |
Array
(
[id] => 3937635
[patent_doc_number] => 05981360
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-09
[patent_title] => 'Assembly procedure for two structures and apparatus produced by the procedure applications to microlasers'
[patent_app_type] => 1
[patent_app_number] => 8/893314
[patent_app_country] => US
[patent_app_date] => 1997-07-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/981/05981360.pdf
[firstpage_image] =>[orig_patent_app_number] => 893314
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/893314 | Assembly procedure for two structures and apparatus produced by the procedure applications to microlasers | Jul 15, 1997 | Issued |
08/893774 | METHOD AND APPARATUS FOR INSITU VAPOR GENERATION | Jul 10, 1997 | Abandoned |
Array
(
[id] => 3942007
[patent_doc_number] => 05946560
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-08-31
[patent_title] => 'Transistor and method of forming the same'
[patent_app_type] => 1
[patent_app_number] => 8/889760
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 889760
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/889760 | Transistor and method of forming the same | Jul 9, 1997 | Issued |
Array
(
[id] => 3944960
[patent_doc_number] => 05953583
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-09-14
[patent_title] => 'Manufacturing method of a thin-film transistor'
[patent_app_type] => 1
[patent_app_number] => 8/887136
[patent_app_country] => US
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[pdf_file] => patents/05/953/05953583.pdf
[firstpage_image] =>[orig_patent_app_number] => 887136
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/887136 | Manufacturing method of a thin-film transistor | Jul 1, 1997 | Issued |
Array
(
[id] => 3993469
[patent_doc_number] => 05985702
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-16
[patent_title] => 'Methods of forming conductive polysilicon lines and bottom gated thin film transistors, and conductive polysilicon lines and thin film transistors'
[patent_app_type] => 1
[patent_app_number] => 8/882596
[patent_app_country] => US
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[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/985/05985702.pdf
[firstpage_image] =>[orig_patent_app_number] => 882596
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/882596 | Methods of forming conductive polysilicon lines and bottom gated thin film transistors, and conductive polysilicon lines and thin film transistors | Jun 24, 1997 | Issued |
Array
(
[id] => 4016645
[patent_doc_number] => 05923997
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-07-13
[patent_title] => 'Semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 8/877306
[patent_app_country] => US
[patent_app_date] => 1997-06-17
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/923/05923997.pdf
[firstpage_image] =>[orig_patent_app_number] => 877306
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/877306 | Semiconductor device | Jun 16, 1997 | Issued |
Array
(
[id] => 3944450
[patent_doc_number] => 05976994
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-02
[patent_title] => 'Method and system for locally annealing a microstructure formed on a substrate and device formed thereby'
[patent_app_type] => 1
[patent_app_number] => 8/874785
[patent_app_country] => US
[patent_app_date] => 1997-06-13
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/976/05976994.pdf
[firstpage_image] =>[orig_patent_app_number] => 874785
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/874785 | Method and system for locally annealing a microstructure formed on a substrate and device formed thereby | Jun 12, 1997 | Issued |
Array
(
[id] => 4050750
[patent_doc_number] => 05943592
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-08-24
[patent_title] => 'Method of making a MIS transistor'
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[patent_app_number] => 8/876096
[patent_app_country] => US
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[pdf_file] => patents/05/943/05943592.pdf
[firstpage_image] =>[orig_patent_app_number] => 876096
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/876096 | Method of making a MIS transistor | Jun 9, 1997 | Issued |
Array
(
[id] => 3993999
[patent_doc_number] => 05918110
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-06-29
[patent_title] => 'Method for manufacturing a combination of a pressure sensor and an electrochemical sensor'
[patent_app_type] => 1
[patent_app_number] => 8/866414
[patent_app_country] => US
[patent_app_date] => 1997-05-30
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[pdf_file] => patents/05/918/05918110.pdf
[firstpage_image] =>[orig_patent_app_number] => 866414
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/866414 | Method for manufacturing a combination of a pressure sensor and an electrochemical sensor | May 29, 1997 | Issued |