Search

Michael P Barker

Examiner (ID: 12455, Phone: (571)272-0303 , Office: P/1626 )

Most Active Art Unit
1626
Art Unit(s)
OPQA, 1626, 1655
Total Applications
1330
Issued Applications
1012
Pending Applications
61
Abandoned Applications
257

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4070131 [patent_doc_number] => 05970325 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-19 [patent_title] => 'Thin-film switching device having chlorine-containing active region and methods of fabrication therefor' [patent_app_type] => 1 [patent_app_number] => 8/858974 [patent_app_country] => US [patent_app_date] => 1997-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 4510 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/970/05970325.pdf [firstpage_image] =>[orig_patent_app_number] => 858974 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/858974
Thin-film switching device having chlorine-containing active region and methods of fabrication therefor May 19, 1997 Issued
Array ( [id] => 3938243 [patent_doc_number] => 05981404 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Multilayer ONO structure' [patent_app_type] => 1 [patent_app_number] => 8/857734 [patent_app_country] => US [patent_app_date] => 1997-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 5549 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/981/05981404.pdf [firstpage_image] =>[orig_patent_app_number] => 857734 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/857734
Multilayer ONO structure May 15, 1997 Issued
Array ( [id] => 3993287 [patent_doc_number] => 05985691 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'Method of making compound semiconductor films and making related electronic devices' [patent_app_type] => 1 [patent_app_number] => 8/857665 [patent_app_country] => US [patent_app_date] => 1997-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 9816 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/985/05985691.pdf [firstpage_image] =>[orig_patent_app_number] => 857665 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/857665
Method of making compound semiconductor films and making related electronic devices May 15, 1997 Issued
Array ( [id] => 3994091 [patent_doc_number] => 05918116 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-29 [patent_title] => 'Process for forming gate oxides possessing different thicknesses on a semiconductor substrate' [patent_app_type] => 1 [patent_app_number] => 8/853210 [patent_app_country] => US [patent_app_date] => 1997-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 17 [patent_no_of_words] => 2306 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/918/05918116.pdf [firstpage_image] =>[orig_patent_app_number] => 853210 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/853210
Process for forming gate oxides possessing different thicknesses on a semiconductor substrate May 8, 1997 Issued
Array ( [id] => 3943934 [patent_doc_number] => 05976959 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Method for forming large area or selective area SOI' [patent_app_type] => 1 [patent_app_number] => 8/850134 [patent_app_country] => US [patent_app_date] => 1997-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 2977 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/976/05976959.pdf [firstpage_image] =>[orig_patent_app_number] => 850134 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/850134
Method for forming large area or selective area SOI Apr 30, 1997 Issued
Array ( [id] => 4218978 [patent_doc_number] => 06040224 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-21 [patent_title] => 'Method of manufacturing semiconductor devices' [patent_app_type] => 1 [patent_app_number] => 8/841626 [patent_app_country] => US [patent_app_date] => 1997-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 2777 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/040/06040224.pdf [firstpage_image] =>[orig_patent_app_number] => 841626 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/841626
Method of manufacturing semiconductor devices Apr 29, 1997 Issued
Array ( [id] => 4029224 [patent_doc_number] => 05994170 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'Silicon segment programming method' [patent_app_type] => 1 [patent_app_number] => 8/845654 [patent_app_country] => US [patent_app_date] => 1997-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 5826 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/994/05994170.pdf [firstpage_image] =>[orig_patent_app_number] => 845654 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/845654
Silicon segment programming method Apr 24, 1997 Issued
Array ( [id] => 3935393 [patent_doc_number] => 05972784 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-26 [patent_title] => 'Arrangement, dopant source, and method for making solar cells' [patent_app_type] => 1 [patent_app_number] => 8/839969 [patent_app_country] => US [patent_app_date] => 1997-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7189 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/972/05972784.pdf [firstpage_image] =>[orig_patent_app_number] => 839969 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/839969
Arrangement, dopant source, and method for making solar cells Apr 23, 1997 Issued
Array ( [id] => 3952688 [patent_doc_number] => 05940690 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-17 [patent_title] => 'Production method for a thin film semiconductor device with an alignment marker made out of the same layer as the active region' [patent_app_type] => 1 [patent_app_number] => 8/844856 [patent_app_country] => US [patent_app_date] => 1997-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 46 [patent_no_of_words] => 9521 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/940/05940690.pdf [firstpage_image] =>[orig_patent_app_number] => 844856 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/844856
Production method for a thin film semiconductor device with an alignment marker made out of the same layer as the active region Apr 22, 1997 Issued
Array ( [id] => 3994051 [patent_doc_number] => 05985741 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'Semiconductor device and method of fabricating the same' [patent_app_type] => 1 [patent_app_number] => 8/821656 [patent_app_country] => US [patent_app_date] => 1997-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 7469 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/985/05985741.pdf [firstpage_image] =>[orig_patent_app_number] => 821656 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/821656
Semiconductor device and method of fabricating the same Mar 19, 1997 Issued
Array ( [id] => 4039100 [patent_doc_number] => 05926723 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-20 [patent_title] => 'Generation of a loose planarization mask having relaxed boundary conditions for use in shallow trench isolation processes' [patent_app_type] => 1 [patent_app_number] => 8/813008 [patent_app_country] => US [patent_app_date] => 1997-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 25 [patent_no_of_words] => 5071 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/926/05926723.pdf [firstpage_image] =>[orig_patent_app_number] => 813008 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/813008
Generation of a loose planarization mask having relaxed boundary conditions for use in shallow trench isolation processes Mar 3, 1997 Issued
Array ( [id] => 4042439 [patent_doc_number] => 05874349 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-23 [patent_title] => 'Multi-layer structure for II-VI group compound semiconductor and method for forming the same' [patent_app_type] => 1 [patent_app_number] => 8/792130 [patent_app_country] => US [patent_app_date] => 1997-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3011 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/874/05874349.pdf [firstpage_image] =>[orig_patent_app_number] => 792130 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/792130
Multi-layer structure for II-VI group compound semiconductor and method for forming the same Jan 30, 1997 Issued
Array ( [id] => 4222389 [patent_doc_number] => 06010952 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-04 [patent_title] => 'Process for forming metal silicide contacts using amorphization of exposed silicon while minimizing device degradation' [patent_app_type] => 1 [patent_app_number] => 8/787992 [patent_app_country] => US [patent_app_date] => 1997-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2565 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/010/06010952.pdf [firstpage_image] =>[orig_patent_app_number] => 787992 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/787992
Process for forming metal silicide contacts using amorphization of exposed silicon while minimizing device degradation Jan 22, 1997 Issued
Array ( [id] => 3968657 [patent_doc_number] => 05904508 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-18 [patent_title] => 'Semiconductor device and a method of manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 8/786188 [patent_app_country] => US [patent_app_date] => 1997-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 36 [patent_no_of_words] => 6267 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/904/05904508.pdf [firstpage_image] =>[orig_patent_app_number] => 786188 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/786188
Semiconductor device and a method of manufacturing the same Jan 20, 1997 Issued
Array ( [id] => 3941707 [patent_doc_number] => 05989970 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-23 [patent_title] => 'Method for fabricating semiconductor device having thin-film resistor' [patent_app_type] => 1 [patent_app_number] => 8/774796 [patent_app_country] => US [patent_app_date] => 1996-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 2397 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/989/05989970.pdf [firstpage_image] =>[orig_patent_app_number] => 774796 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/774796
Method for fabricating semiconductor device having thin-film resistor Dec 29, 1996 Issued
Array ( [id] => 4050664 [patent_doc_number] => 05943586 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-24 [patent_title] => 'LED array alignment mark, method and mask for forming same, and LED array alignment method' [patent_app_type] => 1 [patent_app_number] => 8/768184 [patent_app_country] => US [patent_app_date] => 1996-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 24 [patent_no_of_words] => 4555 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/943/05943586.pdf [firstpage_image] =>[orig_patent_app_number] => 768184 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/768184
LED array alignment mark, method and mask for forming same, and LED array alignment method Dec 16, 1996 Issued
Array ( [id] => 3945501 [patent_doc_number] => 05953620 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-14 [patent_title] => 'Method for fabricating a bonded SOI wafer' [patent_app_type] => 1 [patent_app_number] => 8/764588 [patent_app_country] => US [patent_app_date] => 1996-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1774 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/953/05953620.pdf [firstpage_image] =>[orig_patent_app_number] => 764588 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/764588
Method for fabricating a bonded SOI wafer Dec 12, 1996 Issued
Array ( [id] => 4207223 [patent_doc_number] => 06028012 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-22 [patent_title] => 'Process for forming a gate-quality insulating layer on a silicon carbide substrate' [patent_app_type] => 1 [patent_app_number] => 8/760056 [patent_app_country] => US [patent_app_date] => 1996-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3152 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/028/06028012.pdf [firstpage_image] =>[orig_patent_app_number] => 760056 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/760056
Process for forming a gate-quality insulating layer on a silicon carbide substrate Dec 3, 1996 Issued
Array ( [id] => 4090259 [patent_doc_number] => 05966596 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-12 [patent_title] => 'Method of fabricating semiconductor devices by crystallizing amorphous silicon with nickel' [patent_app_type] => 1 [patent_app_number] => 8/757112 [patent_app_country] => US [patent_app_date] => 1996-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 26 [patent_no_of_words] => 8061 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/966/05966596.pdf [firstpage_image] =>[orig_patent_app_number] => 757112 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/757112
Method of fabricating semiconductor devices by crystallizing amorphous silicon with nickel Dec 1, 1996 Issued
Array ( [id] => 3937163 [patent_doc_number] => 05915196 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-22 [patent_title] => 'Method of forming shallow diffusion layers in a semiconductor substrate in the vicinity of a gate electrode' [patent_app_type] => 1 [patent_app_number] => 8/746486 [patent_app_country] => US [patent_app_date] => 1996-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 19 [patent_no_of_words] => 13298 [patent_no_of_claims] => 66 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/915/05915196.pdf [firstpage_image] =>[orig_patent_app_number] => 746486 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/746486
Method of forming shallow diffusion layers in a semiconductor substrate in the vicinity of a gate electrode Nov 11, 1996 Issued
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