Search

Michael P. Ferguson

Examiner (ID: 7246, Phone: (571)272-7081 , Office: P/3679 )

Most Active Art Unit
3679
Art Unit(s)
3629, 3679, 3678, 3619
Total Applications
1903
Issued Applications
1114
Pending Applications
150
Abandoned Applications
660

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20649724 [patent_doc_number] => 12604687 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-14 [patent_title] => Large-area/wafer-scale CMOS-compatible 2D-material intercalation doping tools, processes, and methods, including intercalation doping of synthesized and patterned graphene [patent_app_type] => utility [patent_app_number] => 19/224621 [patent_app_country] => US [patent_app_date] => 2025-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5627 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19224621 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/224621
Large-area/wafer-scale CMOS-compatible 2D-material intercalation doping tools, processes, and methods, including intercalation doping of synthesized and patterned graphene May 29, 2025 Issued
Array ( [id] => 19935038 [patent_doc_number] => 12308246 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-05-20 [patent_title] => Method for manufacturing semiconductor device [patent_app_type] => utility [patent_app_number] => 19/047173 [patent_app_country] => US [patent_app_date] => 2025-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 0 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 336 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19047173 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/047173
Method for manufacturing semiconductor device Feb 5, 2025 Issued
Array ( [id] => 20291351 [patent_doc_number] => 20250316594 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-09 [patent_title] => SEMICONDUCTOR DEVICE INCLUDING BACKSIDE CONTACT STRUCTURE FORMED BASED ON WIDE PLACEHOLDER STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/887789 [patent_app_country] => US [patent_app_date] => 2024-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4240 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18887789 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/887789
Semiconductor device including backside contact structure formed based on wide placeholder structure Sep 16, 2024 Issued
Array ( [id] => 19515779 [patent_doc_number] => 20240347465 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => CONTACT OVER ACTIVE GATE STRUCTURES WITH ETCH STOP LAYERS FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION [patent_app_type] => utility [patent_app_number] => 18/753766 [patent_app_country] => US [patent_app_date] => 2024-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16045 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18753766 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/753766
CONTACT OVER ACTIVE GATE STRUCTURES WITH ETCH STOP LAYERS FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION Jun 24, 2024 Pending
Array ( [id] => 19500337 [patent_doc_number] => 20240339355 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => Air-Replaced Spacer for Self-Aligned Contact Scheme [patent_app_type] => utility [patent_app_number] => 18/743574 [patent_app_country] => US [patent_app_date] => 2024-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9943 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18743574 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/743574
Air-Replaced Spacer for Self-Aligned Contact Scheme Jun 13, 2024 Pending
Array ( [id] => 19467951 [patent_doc_number] => 20240321621 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => FAN-OUT INTERCONNECT STRUCTURE AND METHODS FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/733107 [patent_app_country] => US [patent_app_date] => 2024-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4996 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18733107 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/733107
FAN-OUT INTERCONNECT STRUCTURE AND METHODS FORMING THE SAME Jun 3, 2024 Pending
Array ( [id] => 19467919 [patent_doc_number] => 20240321589 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => PROCESSES TO DEPOSIT AMORPHOUS-SILICON ETCH PROTECTION LINER [patent_app_type] => utility [patent_app_number] => 18/680496 [patent_app_country] => US [patent_app_date] => 2024-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7550 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18680496 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/680496
PROCESSES TO DEPOSIT AMORPHOUS-SILICON ETCH PROTECTION LINER May 30, 2024 Pending
Array ( [id] => 20030830 [patent_doc_number] => 20250169052 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-22 [patent_title] => SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEMS INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/670998 [patent_app_country] => US [patent_app_date] => 2024-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10069 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18670998 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/670998
SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEMS INCLUDING THE SAME May 21, 2024 Pending
Array ( [id] => 20367502 [patent_doc_number] => 20250357314 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-20 [patent_title] => MEMORY DEVICE INCLUDING CANTILEVERED WORD LINES WITH TAB PORTIONS AND METHODS FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/664861 [patent_app_country] => US [patent_app_date] => 2024-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9984 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18664861 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/664861
MEMORY DEVICE INCLUDING CANTILEVERED WORD LINES WITH TAB PORTIONS AND METHODS FOR FORMING THE SAME May 14, 2024 Pending
Array ( [id] => 20365340 [patent_doc_number] => 20250355152 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-20 [patent_title] => INTERFEROMETRIC FILTERS FOR PCAMBER CONVERTERS [patent_app_type] => utility [patent_app_number] => 18/664634 [patent_app_country] => US [patent_app_date] => 2024-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18664634 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/664634
INTERFEROMETRIC FILTERS FOR PCAMBER CONVERTERS May 14, 2024 Pending
Array ( [id] => 19421101 [patent_doc_number] => 20240297225 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-05 [patent_title] => METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/664595 [patent_app_country] => US [patent_app_date] => 2024-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10601 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18664595 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/664595
Method of manufacturing a semiconductor device and a semiconductor device May 14, 2024 Issued
Array ( [id] => 19661987 [patent_doc_number] => 20240429052 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-26 [patent_title] => METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/660507 [patent_app_country] => US [patent_app_date] => 2024-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6239 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18660507 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/660507
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE May 9, 2024 Pending
Array ( [id] => 19407220 [patent_doc_number] => 20240290731 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => WARPAGE-REDUCING SEMICONDUCTOR STRUCTURE AND FABRICATING METHOD OF THE SAME [patent_app_type] => utility [patent_app_number] => 18/660179 [patent_app_country] => US [patent_app_date] => 2024-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3028 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18660179 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/660179
Warpage-reducing semiconductor structure and fabricating method of the same May 8, 2024 Issued
Array ( [id] => 20210969 [patent_doc_number] => 20250280689 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-04 [patent_title] => Display Device [patent_app_type] => utility [patent_app_number] => 18/658448 [patent_app_country] => US [patent_app_date] => 2024-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3514 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18658448 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/658448
Display Device May 7, 2024 Pending
Array ( [id] => 19407064 [patent_doc_number] => 20240290575 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => DETECTION USING SEMICONDUCTOR DETECTOR [patent_app_type] => utility [patent_app_number] => 18/655582 [patent_app_country] => US [patent_app_date] => 2024-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9405 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18655582 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/655582
DETECTION USING SEMICONDUCTOR DETECTOR May 5, 2024 Pending
Array ( [id] => 20244273 [patent_doc_number] => 12424605 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-23 [patent_title] => Hybrid bonding with uniform pattern density [patent_app_type] => utility [patent_app_number] => 18/640167 [patent_app_country] => US [patent_app_date] => 2024-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18640167 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/640167
Hybrid bonding with uniform pattern density Apr 18, 2024 Issued
Array ( [id] => 19866340 [patent_doc_number] => 20250105126 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-27 [patent_title] => DISPLAY DEVICE AND MOBILE ELECTRONIC DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/640300 [patent_app_country] => US [patent_app_date] => 2024-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11919 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18640300 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/640300
DISPLAY DEVICE AND MOBILE ELECTRONIC DEVICE INCLUDING THE SAME Apr 18, 2024 Pending
Array ( [id] => 20119622 [patent_doc_number] => 12369361 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-22 [patent_title] => Integrated circuit including transistors and a method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 18/634295 [patent_app_country] => US [patent_app_date] => 2024-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 21 [patent_no_of_words] => 989 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18634295 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/634295
Integrated circuit including transistors and a method of manufacturing the same Apr 11, 2024 Issued
Array ( [id] => 19364319 [patent_doc_number] => 20240266353 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-08 [patent_title] => GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING DEPOPULATED CHANNEL STRUCTURES USING BOTTOM-UP APPROACH [patent_app_type] => utility [patent_app_number] => 18/625061 [patent_app_country] => US [patent_app_date] => 2024-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15160 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18625061 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/625061
Gate-all-around integrated circuit structures having depopulated channel structures using bottom-up approach Apr 1, 2024 Issued
Array ( [id] => 19546545 [patent_doc_number] => 20240363581 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => WIRE BONDING APPARATUS AND SEMICONDUCTOR PACKAGE MANUFACTURED USING THE SAME [patent_app_type] => utility [patent_app_number] => 18/622131 [patent_app_country] => US [patent_app_date] => 2024-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9652 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18622131 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/622131
WIRE BONDING APPARATUS AND SEMICONDUCTOR PACKAGE MANUFACTURED USING THE SAME Mar 28, 2024 Pending
Menu