Search

Michael P. Mcfadden

Examiner (ID: 3028, Phone: (571)270-5649 , Office: P/2848 )

Most Active Art Unit
2848
Art Unit(s)
2848
Total Applications
1059
Issued Applications
876
Pending Applications
96
Abandoned Applications
127

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11924668 [patent_doc_number] => 09792252 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-17 [patent_title] => 'Incorporating a spatial array into one or more programmable processor cores' [patent_app_type] => utility [patent_app_number] => 14/252101 [patent_app_country] => US [patent_app_date] => 2014-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 4132 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14252101 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/252101
Incorporating a spatial array into one or more programmable processor cores Apr 13, 2014 Issued
Array ( [id] => 10408758 [patent_doc_number] => 20150293767 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-15 [patent_title] => 'ROTATING REGISTER FILE WITH BIT EXPANSION SUPPORT' [patent_app_type] => utility [patent_app_number] => 14/251117 [patent_app_country] => US [patent_app_date] => 2014-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2545 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14251117 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/251117
ROTATING REGISTER FILE WITH BIT EXPANSION SUPPORT Apr 10, 2014 Abandoned
Array ( [id] => 10907487 [patent_doc_number] => 20140310501 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-16 [patent_title] => 'APPARATUS AND METHOD FOR CALCULATING PHYSICAL ADDRESS OF A PROCESSOR REGISTER' [patent_app_type] => utility [patent_app_number] => 14/248731 [patent_app_country] => US [patent_app_date] => 2014-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3968 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14248731 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/248731
APPARATUS AND METHOD FOR CALCULATING PHYSICAL ADDRESS OF A PROCESSOR REGISTER Apr 8, 2014 Abandoned
Array ( [id] => 13212625 [patent_doc_number] => 10120682 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-06 [patent_title] => Virtualization in a bi-endian-mode processor architecture [patent_app_type] => utility [patent_app_number] => 14/193610 [patent_app_country] => US [patent_app_date] => 2014-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8500 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14193610 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/193610
Virtualization in a bi-endian-mode processor architecture Feb 27, 2014 Issued
Array ( [id] => 10046491 [patent_doc_number] => 09086888 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-21 [patent_title] => 'Using a plurality of tables for improving performance in predicting branches in processor instructions' [patent_app_type] => utility [patent_app_number] => 14/174966 [patent_app_country] => US [patent_app_date] => 2014-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 9336 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14174966 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/174966
Using a plurality of tables for improving performance in predicting branches in processor instructions Feb 6, 2014 Issued
Array ( [id] => 9493103 [patent_doc_number] => 20140143509 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-22 [patent_title] => 'METHOD AND DEVICE FOR DATA PROCESSING' [patent_app_type] => utility [patent_app_number] => 14/162704 [patent_app_country] => US [patent_app_date] => 2014-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11506 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14162704 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/162704
METHOD AND DEVICE FOR DATA PROCESSING Jan 22, 2014 Abandoned
Array ( [id] => 9479654 [patent_doc_number] => 20140137117 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-15 [patent_title] => 'VIRTUALIZATION PLANNING SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/158726 [patent_app_country] => US [patent_app_date] => 2014-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5513 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14158726 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/158726
Virtualization planning system Jan 16, 2014 Issued
Array ( [id] => 10293088 [patent_doc_number] => 20150178087 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-25 [patent_title] => 'Predicated Vector Hazard Check Instruction' [patent_app_type] => utility [patent_app_number] => 14/137232 [patent_app_country] => US [patent_app_date] => 2013-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 12126 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14137232 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/137232
Predicated vector hazard check instruction Dec 19, 2013 Issued
Array ( [id] => 11614390 [patent_doc_number] => 09652246 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-05-16 [patent_title] => 'Banked physical register data flow architecture in out-of-order processors' [patent_app_type] => utility [patent_app_number] => 14/137519 [patent_app_country] => US [patent_app_date] => 2013-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7247 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14137519 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/137519
Banked physical register data flow architecture in out-of-order processors Dec 19, 2013 Issued
Array ( [id] => 11070203 [patent_doc_number] => 20160267168 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-15 [patent_title] => 'RESIDUAL DATA IDENTIFICATION' [patent_app_type] => utility [patent_app_number] => 15/033181 [patent_app_country] => US [patent_app_date] => 2013-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6802 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15033181 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/033181
RESIDUAL DATA IDENTIFICATION Dec 18, 2013 Abandoned
Array ( [id] => 11070429 [patent_doc_number] => 20160267393 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-15 [patent_title] => 'METHOD OF CONSTRUCTION AND SELECTION OF PROBALISTIC GRAPHICAL MODELS' [patent_app_type] => utility [patent_app_number] => 15/033159 [patent_app_country] => US [patent_app_date] => 2013-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2584 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15033159 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/033159
METHOD OF CONSTRUCTION AND SELECTION OF PROBALISTIC GRAPHICAL MODELS Oct 29, 2013 Abandoned
Array ( [id] => 9320548 [patent_doc_number] => 20140052886 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-20 [patent_title] => 'All-to-All Comparisons on Architectures Having Limited Storage Space' [patent_app_type] => utility [patent_app_number] => 14/061389 [patent_app_country] => US [patent_app_date] => 2013-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8804 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14061389 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/061389
All-to-all comparisons on architectures having limited storage space Oct 22, 2013 Issued
Array ( [id] => 10228198 [patent_doc_number] => 20150113191 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-23 [patent_title] => 'RESOURCE SERIALIZATION IN A TRANSACTIONAL EXECUTION FACILITY' [patent_app_type] => utility [patent_app_number] => 14/055936 [patent_app_country] => US [patent_app_date] => 2013-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4785 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14055936 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/055936
RESOURCE SERIALIZATION IN A TRANSACTIONAL EXECUTION FACILITY Oct 16, 2013 Abandoned
Array ( [id] => 9386459 [patent_doc_number] => 20140089942 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-27 [patent_title] => 'SYSTEM TO PROFILE AND OPTIMIZE USER SOFTWARE IN A MANAGED RUN-TIME ENVIRONMENT' [patent_app_type] => utility [patent_app_number] => 14/036768 [patent_app_country] => US [patent_app_date] => 2013-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 14552 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14036768 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/036768
System to profile and optimize user software in a managed run-time environment Sep 24, 2013 Issued
Array ( [id] => 9213900 [patent_doc_number] => 20140013077 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-09 [patent_title] => 'EFFICIENT HARDWARE INSTRUCTIONS FOR SINGLE INSTRUCTION MULTIPLE DATA PROCESSORS' [patent_app_type] => utility [patent_app_number] => 14/023249 [patent_app_country] => US [patent_app_date] => 2013-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 12719 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14023249 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/023249
Efficient hardware instructions for processing bit vectors for single instruction multiple data processors Sep 9, 2013 Issued
Array ( [id] => 9213899 [patent_doc_number] => 20140013076 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-09 [patent_title] => 'EFFICIENT HARDWARE INSTRUCTIONS FOR SINGLE INSTRUCTION MULTIPLE DATA PROCESSORS' [patent_app_type] => utility [patent_app_number] => 14/023064 [patent_app_country] => US [patent_app_date] => 2013-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 12944 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14023064 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/023064
Loading values from a value vector into subregisters of a single instruction multiple data register Sep 9, 2013 Issued
Array ( [id] => 11780722 [patent_doc_number] => 09389904 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-07-12 [patent_title] => 'Apparatus, system and method for heterogeneous data sharing' [patent_app_type] => utility [patent_app_number] => 13/955991 [patent_app_country] => US [patent_app_date] => 2013-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5486 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13955991 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/955991
Apparatus, system and method for heterogeneous data sharing Jul 30, 2013 Issued
Array ( [id] => 9150495 [patent_doc_number] => 20130305018 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-14 [patent_title] => 'MFENCE and LFENCE Micro-Architectural Implementation Method and System' [patent_app_type] => utility [patent_app_number] => 13/942660 [patent_app_country] => US [patent_app_date] => 2013-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5347 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13942660 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/942660
MFENCE and LFENCE micro-architectural implementation method and system Jul 14, 2013 Issued
Array ( [id] => 10335333 [patent_doc_number] => 20150220338 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-06 [patent_title] => 'SOFTWARE POLLING ELISION WITH RESTRICTED TRANSACTIONAL MEMORY' [patent_app_type] => utility [patent_app_number] => 14/127988 [patent_app_country] => US [patent_app_date] => 2013-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4685 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14127988 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/127988
SOFTWARE POLLING ELISION WITH RESTRICTED TRANSACTIONAL MEMORY Jun 17, 2013 Abandoned
Array ( [id] => 10228258 [patent_doc_number] => 20150113252 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-23 [patent_title] => 'THREAD CONTROL AND CALLING METHOD OF MULTI-THREAD VIRTUAL PIPELINE (MVP) PROCESSOR, AND PROCESSOR THEREOF' [patent_app_type] => utility [patent_app_number] => 14/353110 [patent_app_country] => US [patent_app_date] => 2013-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5323 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14353110 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/353110
THREAD CONTROL AND CALLING METHOD OF MULTI-THREAD VIRTUAL PIPELINE (MVP) PROCESSOR, AND PROCESSOR THEREOF Jun 6, 2013 Abandoned
Menu