Search

Michael P. Mcfadden

Examiner (ID: 3028, Phone: (571)270-5649 , Office: P/2848 )

Most Active Art Unit
2848
Art Unit(s)
2848
Total Applications
1059
Issued Applications
876
Pending Applications
96
Abandoned Applications
127

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9017357 [patent_doc_number] => 20130232321 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-05 [patent_title] => 'Unpacking Packed Data In Multiple Lanes' [patent_app_type] => utility [patent_app_number] => 13/837908 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8848 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13837908 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/837908
Unpacking packed data in multiple lanes Mar 14, 2013 Issued
Array ( [id] => 10623368 [patent_doc_number] => 09342310 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-17 [patent_title] => 'MFENCE and LFENCE micro-architectural implementation method and system' [patent_app_type] => utility [patent_app_number] => 13/838229 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5259 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13838229 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/838229
MFENCE and LFENCE micro-architectural implementation method and system Mar 14, 2013 Issued
Array ( [id] => 9341442 [patent_doc_number] => 20140068226 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-06 [patent_title] => 'VECTOR INSTRUCTIONS TO ENABLE EFFICIENT SYNCHRONIZATION AND PARALLEL REDUCTION OPERATIONS' [patent_app_type] => utility [patent_app_number] => 13/795234 [patent_app_country] => US [patent_app_date] => 2013-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7586 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13795234 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/795234
Vector instructions to enable efficient synchronization and parallel reduction operations Mar 11, 2013 Issued
Array ( [id] => 9308547 [patent_doc_number] => 20140047221 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-13 [patent_title] => 'FUSING FLAG-PRODUCING AND FLAG-CONSUMING INSTRUCTIONS IN INSTRUCTION PROCESSING CIRCUITS, AND RELATED PROCESSOR SYSTEMS, METHODS, AND COMPUTER-READABLE MEDIA' [patent_app_type] => utility [patent_app_number] => 13/788008 [patent_app_country] => US [patent_app_date] => 2013-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 12197 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13788008 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/788008
FUSING FLAG-PRODUCING AND FLAG-CONSUMING INSTRUCTIONS IN INSTRUCTION PROCESSING CIRCUITS, AND RELATED PROCESSOR SYSTEMS, METHODS, AND COMPUTER-READABLE MEDIA Mar 6, 2013 Abandoned
Array ( [id] => 11465671 [patent_doc_number] => 09582302 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-28 [patent_title] => 'System and method for managing code isolation' [patent_app_type] => utility [patent_app_number] => 13/788259 [patent_app_country] => US [patent_app_date] => 2013-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 9219 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13788259 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/788259
System and method for managing code isolation Mar 6, 2013 Issued
13/787907 PREVENTING EXECUTION OF PARITY-ERROR-INDUCED UNPREDICTABLE INSTRUCTIONS, AND RELATED PROCESSOR SYSTEMS, METHODS, AND COMPUTER-READABLE MEDIA Mar 6, 2013 Abandoned
Array ( [id] => 9036243 [patent_doc_number] => 20130238881 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-12 [patent_title] => 'DATA TRANSMISSION DEVICE, DATA TRANSMISSION METHOD, AND COMPUTER PROGRAM PRODUCT' [patent_app_type] => utility [patent_app_number] => 13/787682 [patent_app_country] => US [patent_app_date] => 2013-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6054 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13787682 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/787682
DATA TRANSMISSION DEVICE, DATA TRANSMISSION METHOD, AND COMPUTER PROGRAM PRODUCT Mar 5, 2013 Abandoned
Array ( [id] => 12173773 [patent_doc_number] => 09891917 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-13 [patent_title] => 'System and method to increase lockstep core availability' [patent_app_type] => utility [patent_app_number] => 13/786550 [patent_app_country] => US [patent_app_date] => 2013-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6206 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13786550 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/786550
System and method to increase lockstep core availability Mar 5, 2013 Issued
Array ( [id] => 11924536 [patent_doc_number] => 09792120 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-17 [patent_title] => 'Anticipated prefetching for a parent core in a multi-core chip' [patent_app_type] => utility [patent_app_number] => 13/785394 [patent_app_country] => US [patent_app_date] => 2013-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4880 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13785394 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/785394
Anticipated prefetching for a parent core in a multi-core chip Mar 4, 2013 Issued
Array ( [id] => 9722979 [patent_doc_number] => 20140258680 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-11 [patent_title] => 'PARALLEL DISPATCH OF COPROCESSOR INSTRUCTIONS IN A MULTI-THREAD PROCESSOR' [patent_app_type] => utility [patent_app_number] => 13/785017 [patent_app_country] => US [patent_app_date] => 2013-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9111 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13785017 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/785017
PARALLEL DISPATCH OF COPROCESSOR INSTRUCTIONS IN A MULTI-THREAD PROCESSOR Mar 4, 2013 Abandoned
Array ( [id] => 9722995 [patent_doc_number] => 20140258696 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-11 [patent_title] => 'STRIDED TARGET ADDRESS PREDICTOR (STAP) FOR INDIRECT BRANCHES' [patent_app_type] => utility [patent_app_number] => 13/784964 [patent_app_country] => US [patent_app_date] => 2013-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3659 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13784964 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/784964
STRIDED TARGET ADDRESS PREDICTOR (STAP) FOR INDIRECT BRANCHES Mar 4, 2013 Abandoned
13/783209 RECONFIGURABLE GRAPH PROCESSOR Feb 28, 2013 Abandoned
Array ( [id] => 9688221 [patent_doc_number] => 20140244986 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-28 [patent_title] => 'SYSTEM AND METHOD TO SELECT A PACKET FORMAT BASED ON A NUMBER OF EXECUTED THREADS' [patent_app_type] => utility [patent_app_number] => 13/776947 [patent_app_country] => US [patent_app_date] => 2013-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 12450 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13776947 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/776947
System and method to select a packet format based on a number of executed threads Feb 25, 2013 Issued
Array ( [id] => 9006124 [patent_doc_number] => 20130227249 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-29 [patent_title] => 'Three-Dimensional Permute Unit for a Single-Instruction Multiple-Data Processor' [patent_app_type] => utility [patent_app_number] => 13/775355 [patent_app_country] => US [patent_app_date] => 2013-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8059 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13775355 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/775355
Three-dimensional permute unit for a single-instruction multiple-data processor Feb 24, 2013 Issued
Array ( [id] => 9688212 [patent_doc_number] => 20140244977 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-28 [patent_title] => 'Deferred Saving of Registers in a Shared Register Pool for a Multithreaded Microprocessor' [patent_app_type] => utility [patent_app_number] => 13/774140 [patent_app_country] => US [patent_app_date] => 2013-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6178 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13774140 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/774140
Deferred Saving of Registers in a Shared Register Pool for a Multithreaded Microprocessor Feb 21, 2013 Abandoned
Array ( [id] => 9688211 [patent_doc_number] => 20140244976 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-28 [patent_title] => 'IT INSTRUCTION PRE-DECODE' [patent_app_type] => utility [patent_app_number] => 13/774093 [patent_app_country] => US [patent_app_date] => 2013-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7951 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13774093 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/774093
IT instruction pre-decode Feb 21, 2013 Issued
Array ( [id] => 9688222 [patent_doc_number] => 20140244987 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-28 [patent_title] => 'Precision Exception Signaling for Multiple Data Architecture' [patent_app_type] => utility [patent_app_number] => 13/773818 [patent_app_country] => US [patent_app_date] => 2013-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4756 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13773818 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/773818
Precision Exception Signaling for Multiple Data Architecture Feb 21, 2013 Abandoned
Array ( [id] => 9176339 [patent_doc_number] => 20130318324 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-28 [patent_title] => 'MINICORE-BASED RECONFIGURABLE PROCESSOR AND METHOD OF FLEXIBLY PROCESSING MULTIPLE DATA USING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/766173 [patent_app_country] => US [patent_app_date] => 2013-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5033 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13766173 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/766173
MINICORE-BASED RECONFIGURABLE PROCESSOR AND METHOD OF FLEXIBLY PROCESSING MULTIPLE DATA USING THE SAME Feb 12, 2013 Abandoned
Array ( [id] => 13817601 [patent_doc_number] => 10185569 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-22 [patent_title] => Precise-restartable parallel execution of programs [patent_app_type] => utility [patent_app_number] => 13/766053 [patent_app_country] => US [patent_app_date] => 2013-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 7851 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 277 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13766053 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/766053
Precise-restartable parallel execution of programs Feb 12, 2013 Issued
Array ( [id] => 11345193 [patent_doc_number] => 09529599 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-12-27 [patent_title] => 'Dynamic propagation with iterative pipeline processing' [patent_app_type] => utility [patent_app_number] => 13/764905 [patent_app_country] => US [patent_app_date] => 2013-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 12062 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13764905 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/764905
Dynamic propagation with iterative pipeline processing Feb 11, 2013 Issued
Menu