Search

Michael P. Mcfadden

Examiner (ID: 3028, Phone: (571)270-5649 , Office: P/2848 )

Most Active Art Unit
2848
Art Unit(s)
2848
Total Applications
1059
Issued Applications
876
Pending Applications
96
Abandoned Applications
127

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11278690 [patent_doc_number] => 09495169 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-15 [patent_title] => 'Predicate trace compression' [patent_app_type] => utility [patent_app_number] => 13/449411 [patent_app_country] => US [patent_app_date] => 2012-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 6841 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13449411 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/449411
Predicate trace compression Apr 17, 2012 Issued
Array ( [id] => 9109891 [patent_doc_number] => 20130283023 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-24 [patent_title] => 'Bimodal Compare Predictor Encoded In Each Compare Instruction' [patent_app_type] => utility [patent_app_number] => 13/449754 [patent_app_country] => US [patent_app_date] => 2012-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4381 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13449754 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/449754
Bimodal Compare Predictor Encoded In Each Compare Instruction Apr 17, 2012 Abandoned
Array ( [id] => 11452111 [patent_doc_number] => 09575754 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-21 [patent_title] => 'Zero cycle move' [patent_app_type] => utility [patent_app_number] => 13/447651 [patent_app_country] => US [patent_app_date] => 2012-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 12066 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 293 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13447651 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/447651
Zero cycle move Apr 15, 2012 Issued
Array ( [id] => 9096406 [patent_doc_number] => 20130275717 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-17 [patent_title] => 'Multi-Tier Data Processing' [patent_app_type] => utility [patent_app_number] => 13/445848 [patent_app_country] => US [patent_app_date] => 2012-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7027 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13445848 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/445848
Multi-Tier Data Processing Apr 11, 2012 Abandoned
Array ( [id] => 8588598 [patent_doc_number] => 20130007419 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-03 [patent_title] => 'COMPUTER IMPLEMENTED METHOD OF ELECTING K EXTREME ENTRIES FROM A LIST USING SEPARATE SECTION COMPARISONS' [patent_app_type] => utility [patent_app_number] => 13/445728 [patent_app_country] => US [patent_app_date] => 2012-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7915 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13445728 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/445728
Computer implemented method of electing K extreme entries from a list using separate section comparisons Apr 11, 2012 Issued
Array ( [id] => 10901451 [patent_doc_number] => 08924694 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-30 [patent_title] => 'Packet data modification processor' [patent_app_type] => utility [patent_app_number] => 13/444700 [patent_app_country] => US [patent_app_date] => 2012-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 48 [patent_figures_cnt] => 48 [patent_no_of_words] => 14175 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 354 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13444700 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/444700
Packet data modification processor Apr 10, 2012 Issued
Array ( [id] => 11775071 [patent_doc_number] => 09383998 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-07-05 [patent_title] => 'MFENCE and LFENCE micro-architectural implementation method and system' [patent_app_type] => utility [patent_app_number] => 13/440096 [patent_app_country] => US [patent_app_date] => 2012-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 5 [patent_no_of_words] => 5187 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13440096 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/440096
MFENCE and LFENCE micro-architectural implementation method and system Apr 4, 2012 Issued
Array ( [id] => 9618228 [patent_doc_number] => 20140208085 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-24 [patent_title] => 'INSTRUCTION AND LOGIC TO EFFICIENTLY MONITOR LOOP TRIP COUNT' [patent_app_type] => utility [patent_app_number] => 13/996861 [patent_app_country] => US [patent_app_date] => 2012-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 15995 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13996861 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/996861
Instruction and logic to monitor loop trip count and remove loop optimizations Mar 29, 2012 Issued
Array ( [id] => 9137202 [patent_doc_number] => 20130297917 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-07 [patent_title] => 'SYSTEM AND METHOD FOR REAL TIME INSTRUCTION TRACING' [patent_app_type] => utility [patent_app_number] => 13/997016 [patent_app_country] => US [patent_app_date] => 2012-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8410 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13997016 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/997016
System and method for real time instruction tracing Mar 29, 2012 Issued
Array ( [id] => 8303310 [patent_doc_number] => 20120185870 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-19 [patent_title] => 'All-to-All Comparisons on Architectures Having Limited Storage Space' [patent_app_type] => utility [patent_app_number] => 13/429915 [patent_app_country] => US [patent_app_date] => 2012-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8869 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13429915 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/429915
All-to-all comparisons on architectures having limited storage space Mar 25, 2012 Issued
Array ( [id] => 8504529 [patent_doc_number] => 20120303936 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-29 [patent_title] => 'DATA PROCESSING SYSTEM WITH LATENCY TOLERANCE EXECUTION' [patent_app_type] => utility [patent_app_number] => 13/419531 [patent_app_country] => US [patent_app_date] => 2012-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 17448 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13419531 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/419531
Data processing system with latency tolerance execution Mar 13, 2012 Issued
Array ( [id] => 9017358 [patent_doc_number] => 20130232322 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-05 [patent_title] => 'UNIFORM LOAD PROCESSING FOR PARALLEL THREAD SUB-SETS' [patent_app_type] => utility [patent_app_number] => 13/412438 [patent_app_country] => US [patent_app_date] => 2012-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10505 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13412438 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/412438
Uniform load processing for parallel thread sub-sets Mar 4, 2012 Issued
Array ( [id] => 8395604 [patent_doc_number] => 20120233446 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-13 [patent_title] => 'Program-Instruction-Controlled Instruction Flow Supervision' [patent_app_type] => utility [patent_app_number] => 13/409369 [patent_app_country] => US [patent_app_date] => 2012-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 13590 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13409369 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/409369
Program-instruction-controlled instruction flow supervision Feb 29, 2012 Issued
Array ( [id] => 10091872 [patent_doc_number] => 09128697 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-09-08 [patent_title] => 'Computer numerical storage format with precision type indicator' [patent_app_type] => utility [patent_app_number] => 13/403618 [patent_app_country] => US [patent_app_date] => 2012-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 6993 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13403618 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/403618
Computer numerical storage format with precision type indicator Feb 22, 2012 Issued
Array ( [id] => 10091706 [patent_doc_number] => 09128531 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-08 [patent_title] => 'Operand special case handling for multi-lane processing' [patent_app_type] => utility [patent_app_number] => 13/402280 [patent_app_country] => US [patent_app_date] => 2012-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4597 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13402280 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/402280
Operand special case handling for multi-lane processing Feb 21, 2012 Issued
Array ( [id] => 9604825 [patent_doc_number] => 20140201506 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-17 [patent_title] => 'METHOD FOR DETERMINING INSTRUCTION ORDER USING TRIGGERS' [patent_app_type] => utility [patent_app_number] => 13/997021 [patent_app_country] => US [patent_app_date] => 2011-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3554 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13997021 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/997021
METHOD FOR DETERMINING INSTRUCTION ORDER USING TRIGGERS Dec 29, 2011 Abandoned
Array ( [id] => 9618223 [patent_doc_number] => 20140208080 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-24 [patent_title] => 'APPARATUS AND METHOD FOR DOWN CONVERSION OF DATA TYPES' [patent_app_type] => utility [patent_app_number] => 13/997006 [patent_app_country] => US [patent_app_date] => 2011-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 14863 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13997006 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/997006
Apparatus and method for down conversion of data types Dec 22, 2011 Issued
Array ( [id] => 13029171 [patent_doc_number] => 10037205 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-31 [patent_title] => Instruction and logic to provide vector blend and permute functionality [patent_app_type] => utility [patent_app_number] => 13/977734 [patent_app_country] => US [patent_app_date] => 2011-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 28 [patent_no_of_words] => 15961 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 313 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13977734 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/977734
Instruction and logic to provide vector blend and permute functionality Dec 22, 2011 Issued
Array ( [id] => 11931550 [patent_doc_number] => 09798548 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-24 [patent_title] => 'Methods and apparatus for scheduling instructions using pre-decode data' [patent_app_type] => utility [patent_app_number] => 13/333879 [patent_app_country] => US [patent_app_date] => 2011-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 12391 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13333879 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/333879
Methods and apparatus for scheduling instructions using pre-decode data Dec 20, 2011 Issued
Array ( [id] => 8568703 [patent_doc_number] => 20120331274 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-27 [patent_title] => 'Instruction Execution' [patent_app_type] => utility [patent_app_number] => 13/333939 [patent_app_country] => US [patent_app_date] => 2011-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3182 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13333939 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/333939
Executing an instruction set using a prefix to interpret an operator field as either a first or a second operator field Dec 20, 2011 Issued
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