Search

Michael P. Mcfadden

Examiner (ID: 3028, Phone: (571)270-5649 , Office: P/2848 )

Most Active Art Unit
2848
Art Unit(s)
2848
Total Applications
1059
Issued Applications
876
Pending Applications
96
Abandoned Applications
127

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7785795 [patent_doc_number] => 20120047351 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-23 [patent_title] => 'DATA PROCESSING SYSTEM HAVING SELECTIVE REDUNDANCY AND METHOD THEREFOR' [patent_app_type] => utility [patent_app_number] => 12/858599 [patent_app_country] => US [patent_app_date] => 2010-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5428 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20120047351.pdf [firstpage_image] =>[orig_patent_app_number] => 12858599 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/858599
Data processing system having selective redundancy and method therefor Aug 17, 2010 Issued
Array ( [id] => 6031480 [patent_doc_number] => 20110055522 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-03 [patent_title] => 'REQUEST CONTROL DEVICE, REQUEST CONTROL METHOD AND ASSOCIATED PROCESSORS' [patent_app_type] => utility [patent_app_number] => 12/858588 [patent_app_country] => US [patent_app_date] => 2010-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7879 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20110055522.pdf [firstpage_image] =>[orig_patent_app_number] => 12858588 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/858588
Request control device, request control method and associated processors Aug 17, 2010 Issued
Array ( [id] => 7746852 [patent_doc_number] => 20120023315 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-26 [patent_title] => 'Generating Hardware Events Via the Instruction Stream for Microprocessor Verification' [patent_app_type] => utility [patent_app_number] => 12/843594 [patent_app_country] => US [patent_app_date] => 2010-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5876 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20120023315.pdf [firstpage_image] =>[orig_patent_app_number] => 12843594 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/843594
Generating hardware events via the instruction stream for microprocessor verification Jul 25, 2010 Issued
Array ( [id] => 7671556 [patent_doc_number] => 20110320825 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-29 [patent_title] => 'FUNCTION VIRTUALIZATION FACILITY FOR FUNCTION QUERY OF A PROCESSOR' [patent_app_type] => utility [patent_app_number] => 12/822358 [patent_app_country] => US [patent_app_date] => 2010-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 21803 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12822358 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/822358
Function virtualization facility for function query of a processor Jun 23, 2010 Issued
Array ( [id] => 12291213 [patent_doc_number] => 09934079 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-03 [patent_title] => Fast remote communication and computation between processors using store and load operations on direct core-to-core memory [patent_app_type] => utility [patent_app_number] => 12/789082 [patent_app_country] => US [patent_app_date] => 2010-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 9146 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12789082 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/789082
Fast remote communication and computation between processors using store and load operations on direct core-to-core memory May 26, 2010 Issued
Array ( [id] => 7582265 [patent_doc_number] => 20110296148 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-01 [patent_title] => 'Transactional Memory System Supporting Unbroken Suspended Execution' [patent_app_type] => utility [patent_app_number] => 12/788351 [patent_app_country] => US [patent_app_date] => 2010-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11964 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0296/20110296148.pdf [firstpage_image] =>[orig_patent_app_number] => 12788351 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/788351
Transactional memory system supporting unbroken suspended execution May 26, 2010 Issued
Array ( [id] => 7582257 [patent_doc_number] => 20110296140 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-01 [patent_title] => 'RISC processor register expansion method' [patent_app_type] => utility [patent_app_number] => 12/801131 [patent_app_country] => US [patent_app_date] => 2010-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3639 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0296/20110296140.pdf [firstpage_image] =>[orig_patent_app_number] => 12801131 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/801131
RISC processor register expansion method May 24, 2010 Abandoned
Array ( [id] => 8060543 [patent_doc_number] => 20110246748 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-06 [patent_title] => 'Managing Sensor and Actuator Data for a Processor and Service Processor Located on a Common Socket' [patent_app_type] => utility [patent_app_number] => 12/755083 [patent_app_country] => US [patent_app_date] => 2010-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 7897 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0246/20110246748.pdf [firstpage_image] =>[orig_patent_app_number] => 12755083 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/755083
Managing sensor and actuator data for a processor and service processor located on a common socket Apr 5, 2010 Issued
Array ( [id] => 6167472 [patent_doc_number] => 20110161977 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-30 [patent_title] => 'METHOD AND DEVICE FOR DATA PROCESSING' [patent_app_type] => utility [patent_app_number] => 12/729932 [patent_app_country] => US [patent_app_date] => 2010-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11507 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0161/20110161977.pdf [firstpage_image] =>[orig_patent_app_number] => 12729932 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/729932
METHOD AND DEVICE FOR DATA PROCESSING Mar 22, 2010 Abandoned
Array ( [id] => 6646564 [patent_doc_number] => 20100174868 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-08 [patent_title] => 'Processor device having a sequential data processing unit and an arrangement of data processing elements' [patent_app_type] => utility [patent_app_number] => 12/729090 [patent_app_country] => US [patent_app_date] => 2010-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11438 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0174/20100174868.pdf [firstpage_image] =>[orig_patent_app_number] => 12729090 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/729090
Processor device having a sequential data processing unit and an arrangement of data processing elements Mar 21, 2010 Abandoned
Array ( [id] => 5940013 [patent_doc_number] => 20110213935 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-01 [patent_title] => 'Data processing apparatus and method for switching a workload between first and second processing circuitry' [patent_app_type] => utility [patent_app_number] => 12/659235 [patent_app_country] => US [patent_app_date] => 2010-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 13688 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0213/20110213935.pdf [firstpage_image] =>[orig_patent_app_number] => 12659235 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/659235
Data processing apparatus and method for switching a workload between first and second processing circuitry Feb 28, 2010 Abandoned
Array ( [id] => 6006035 [patent_doc_number] => 20110119445 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-19 [patent_title] => 'HEAP/STACK GUARD PAGES USING A WAKEUP UNIT' [patent_app_type] => utility [patent_app_number] => 12/696817 [patent_app_country] => US [patent_app_date] => 2010-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6080 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20110119445.pdf [firstpage_image] =>[orig_patent_app_number] => 12696817 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/696817
Heap/stack guard pages using a wakeup unit Jan 28, 2010 Issued
Array ( [id] => 8985101 [patent_doc_number] => 08516231 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-20 [patent_title] => 'Interrupt handling apparatus and method for equal-model processor and processor including the interrupt handling apparatus' [patent_app_type] => utility [patent_app_number] => 12/695266 [patent_app_country] => US [patent_app_date] => 2010-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 5810 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12695266 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/695266
Interrupt handling apparatus and method for equal-model processor and processor including the interrupt handling apparatus Jan 27, 2010 Issued
Array ( [id] => 10098693 [patent_doc_number] => 09135005 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-15 [patent_title] => 'History and alignment based cracking for store multiple instructions for optimizing operand store compare penalties' [patent_app_type] => utility [patent_app_number] => 12/695687 [patent_app_country] => US [patent_app_date] => 2010-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 8950 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12695687 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/695687
History and alignment based cracking for store multiple instructions for optimizing operand store compare penalties Jan 27, 2010 Issued
Array ( [id] => 9486475 [patent_doc_number] => 08732437 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-05-20 [patent_title] => 'Low-overhead misalignment and reformatting support for SIMD' [patent_app_type] => utility [patent_app_number] => 12/693634 [patent_app_country] => US [patent_app_date] => 2010-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 4908 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12693634 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/693634
Low-overhead misalignment and reformatting support for SIMD Jan 25, 2010 Issued
Array ( [id] => 6554251 [patent_doc_number] => 20100205387 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-12 [patent_title] => 'APPARATUS UTILIZING EFFICIENT HARDWARE IMPLEMENTATION OF SHADOW REGISTERS AND METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/690719 [patent_app_country] => US [patent_app_date] => 2010-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7964 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0205/20100205387.pdf [firstpage_image] =>[orig_patent_app_number] => 12690719 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/690719
Apparatus utilizing efficient hardware implementation of shadow registers and method thereof Jan 19, 2010 Issued
Array ( [id] => 6181881 [patent_doc_number] => 20110179254 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-21 [patent_title] => 'LIMITING SPECULATIVE INSTRUCTION FETCHING IN A PROCESSOR' [patent_app_type] => utility [patent_app_number] => 12/688633 [patent_app_country] => US [patent_app_date] => 2010-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8418 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0179/20110179254.pdf [firstpage_image] =>[orig_patent_app_number] => 12688633 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/688633
LIMITING SPECULATIVE INSTRUCTION FETCHING IN A PROCESSOR Jan 14, 2010 Abandoned
Array ( [id] => 6181889 [patent_doc_number] => 20110179258 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-21 [patent_title] => 'PRECISE DATA RETURN HANDLING IN SPECULATIVE PROCESSORS' [patent_app_type] => utility [patent_app_number] => 12/688679 [patent_app_country] => US [patent_app_date] => 2010-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7783 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0179/20110179258.pdf [firstpage_image] =>[orig_patent_app_number] => 12688679 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/688679
Precise data return handling in speculative processors Jan 14, 2010 Issued
Array ( [id] => 6234236 [patent_doc_number] => 20100185834 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-22 [patent_title] => 'Data Storing Method and Processor Using the Same' [patent_app_type] => utility [patent_app_number] => 12/688071 [patent_app_country] => US [patent_app_date] => 2010-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4155 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0185/20100185834.pdf [firstpage_image] =>[orig_patent_app_number] => 12688071 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/688071
Data Storing Method and Processor Using the Same Jan 14, 2010 Abandoned
Array ( [id] => 6409255 [patent_doc_number] => 20100180101 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-15 [patent_title] => 'Method for Executing One or More Programs on a Multi-Core Processor and Many-Core Processor' [patent_app_type] => utility [patent_app_number] => 12/685416 [patent_app_country] => US [patent_app_date] => 2010-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8374 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0180/20100180101.pdf [firstpage_image] =>[orig_patent_app_number] => 12685416 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/685416
Method for Executing One or More Programs on a Multi-Core Processor and Many-Core Processor Jan 10, 2010 Abandoned
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