Search

Michael P. Mcfadden

Examiner (ID: 3028, Phone: (571)270-5649 , Office: P/2848 )

Most Active Art Unit
2848
Art Unit(s)
2848
Total Applications
1059
Issued Applications
876
Pending Applications
96
Abandoned Applications
127

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6191136 [patent_doc_number] => 20110173420 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-14 [patent_title] => 'PROCESSOR RESUME UNIT' [patent_app_type] => utility [patent_app_number] => 12/684852 [patent_app_country] => US [patent_app_date] => 2010-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7114 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0173/20110173420.pdf [firstpage_image] =>[orig_patent_app_number] => 12684852 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/684852
PROCESSOR RESUME UNIT Jan 7, 2010 Abandoned
Array ( [id] => 6191219 [patent_doc_number] => 20110173503 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-14 [patent_title] => 'HARDWARE ENABLED PERFORMANCE COUNTERS WITH SUPPORT FOR OPERATING SYSTEM CONTEXT SWITCHING' [patent_app_type] => utility [patent_app_number] => 12/684190 [patent_app_country] => US [patent_app_date] => 2010-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6464 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0173/20110173503.pdf [firstpage_image] =>[orig_patent_app_number] => 12684190 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/684190
Hardware enabled performance counters with support for operating system context switching Jan 7, 2010 Issued
Array ( [id] => 5976430 [patent_doc_number] => 20110153991 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-23 [patent_title] => 'DUAL ISSUING OF COMPLEX INSTRUCTION SET INSTRUCTIONS' [patent_app_type] => utility [patent_app_number] => 12/645716 [patent_app_country] => US [patent_app_date] => 2009-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6110 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20110153991.pdf [firstpage_image] =>[orig_patent_app_number] => 12645716 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/645716
Dual issuing of complex instruction set instructions Dec 22, 2009 Issued
Array ( [id] => 12474849 [patent_doc_number] => 09990201 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-05 [patent_title] => Multiplication instruction for which execution completes without writing a carry flag [patent_app_type] => utility [patent_app_number] => 12/645383 [patent_app_country] => US [patent_app_date] => 2009-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 8081 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12645383 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/645383
Multiplication instruction for which execution completes without writing a carry flag Dec 21, 2009 Issued
Array ( [id] => 9885917 [patent_doc_number] => 08972702 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-03 [patent_title] => 'Systems and methods for power management in a high performance computing (HPC) cluster' [patent_app_type] => utility [patent_app_number] => 12/627589 [patent_app_country] => US [patent_app_date] => 2009-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4781 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12627589 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/627589
Systems and methods for power management in a high performance computing (HPC) cluster Nov 29, 2009 Issued
Array ( [id] => 6619612 [patent_doc_number] => 20100064106 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-11 [patent_title] => 'DATA PROCESSOR AND DATA PROCESSING SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/546672 [patent_app_country] => US [patent_app_date] => 2009-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9688 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0064/20100064106.pdf [firstpage_image] =>[orig_patent_app_number] => 12546672 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/546672
DATA PROCESSOR AND DATA PROCESSING SYSTEM Aug 23, 2009 Abandoned
Array ( [id] => 6510357 [patent_doc_number] => 20100011196 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-14 [patent_title] => 'Method and program network for exception handling' [patent_app_type] => utility [patent_app_number] => 12/499844 [patent_app_country] => US [patent_app_date] => 2009-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2675 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0011/20100011196.pdf [firstpage_image] =>[orig_patent_app_number] => 12499844 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/499844
Method and program network for exception handling Jul 8, 2009 Abandoned
Array ( [id] => 6262664 [patent_doc_number] => 20100031002 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-04 [patent_title] => 'SIMD MICROPROCESSOR AND OPERATION METHOD' [patent_app_type] => utility [patent_app_number] => 12/495853 [patent_app_country] => US [patent_app_date] => 2009-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5196 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0031/20100031002.pdf [firstpage_image] =>[orig_patent_app_number] => 12495853 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/495853
SIMD MICROPROCESSOR AND OPERATION METHOD Jun 30, 2009 Abandoned
Array ( [id] => 8775410 [patent_doc_number] => 08429386 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-23 [patent_title] => 'Dynamic tag allocation in a multithreaded out-of-order processor' [patent_app_type] => utility [patent_app_number] => 12/494532 [patent_app_country] => US [patent_app_date] => 2009-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 15729 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 292 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12494532 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/494532
Dynamic tag allocation in a multithreaded out-of-order processor Jun 29, 2009 Issued
Array ( [id] => 10046475 [patent_doc_number] => 09086872 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-21 [patent_title] => 'Unpacking packed data in multiple lanes' [patent_app_type] => utility [patent_app_number] => 12/494667 [patent_app_country] => US [patent_app_date] => 2009-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 8815 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12494667 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/494667
Unpacking packed data in multiple lanes Jun 29, 2009 Issued
Array ( [id] => 6362694 [patent_doc_number] => 20100332792 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-30 [patent_title] => 'Integrated Vector-Scalar Processor' [patent_app_type] => utility [patent_app_number] => 12/495246 [patent_app_country] => US [patent_app_date] => 2009-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7650 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0332/20100332792.pdf [firstpage_image] =>[orig_patent_app_number] => 12495246 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/495246
Integrated Vector-Scalar Processor Jun 29, 2009 Abandoned
Array ( [id] => 6491526 [patent_doc_number] => 20100042817 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-18 [patent_title] => 'SHIFT-IN-RIGHT INSTRUCTIONS FOR PROCESSING VECTORS' [patent_app_type] => utility [patent_app_number] => 12/495643 [patent_app_country] => US [patent_app_date] => 2009-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 34204 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20100042817.pdf [firstpage_image] =>[orig_patent_app_number] => 12495643 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/495643
Shift-in-right instructions for processing vectors Jun 29, 2009 Issued
Array ( [id] => 6491544 [patent_doc_number] => 20100042818 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-18 [patent_title] => 'COPY-PROPAGATE, PROPAGATE-POST, AND PROPAGATE-PRIOR INSTRUCTIONS FOR PROCESSING VECTORS' [patent_app_type] => utility [patent_app_number] => 12/495656 [patent_app_country] => US [patent_app_date] => 2009-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 36977 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20100042818.pdf [firstpage_image] =>[orig_patent_app_number] => 12495656 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/495656
Copy-propagate, propagate-post, and propagate-prior instructions for processing vectors Jun 29, 2009 Issued
Array ( [id] => 6362810 [patent_doc_number] => 20100332810 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-30 [patent_title] => 'Reconfigurable Functional Unit Having Instruction Context Storage Circuitry To Support Speculative Execution of Instructions' [patent_app_type] => utility [patent_app_number] => 12/495604 [patent_app_country] => US [patent_app_date] => 2009-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 4485 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0332/20100332810.pdf [firstpage_image] =>[orig_patent_app_number] => 12495604 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/495604
Reconfigurable Functional Unit Having Instruction Context Storage Circuitry To Support Speculative Execution of Instructions Jun 29, 2009 Abandoned
Array ( [id] => 10536541 [patent_doc_number] => 09262171 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-16 [patent_title] => 'Dependency matrix for the determination of load dependencies' [patent_app_type] => utility [patent_app_number] => 12/495025 [patent_app_country] => US [patent_app_date] => 2009-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 16424 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12495025 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/495025
Dependency matrix for the determination of load dependencies Jun 29, 2009 Issued
Array ( [id] => 6491381 [patent_doc_number] => 20100042807 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-18 [patent_title] => 'INCREMENT-PROPAGATE AND DECREMENT-PROPAGATE INSTRUCTIONS FOR PROCESSING VECTORS' [patent_app_type] => utility [patent_app_number] => 12/495631 [patent_app_country] => US [patent_app_date] => 2009-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 35180 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20100042807.pdf [firstpage_image] =>[orig_patent_app_number] => 12495631 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/495631
Increment-propagate and decrement-propagate instructions for processing vectors Jun 29, 2009 Issued
Array ( [id] => 10015166 [patent_doc_number] => 09058180 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-16 [patent_title] => 'Unified high-frequency out-of-order pick queue with support for triggering early issue of speculative instructions' [patent_app_type] => utility [patent_app_number] => 12/493743 [patent_app_country] => US [patent_app_date] => 2009-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 15604 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12493743 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/493743
Unified high-frequency out-of-order pick queue with support for triggering early issue of speculative instructions Jun 28, 2009 Issued
Array ( [id] => 6387888 [patent_doc_number] => 20100082948 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-01 [patent_title] => 'CHANNEL COMMAND WORD PRE-FETCHING APPARATUS' [patent_app_type] => utility [patent_app_number] => 12/493951 [patent_app_country] => US [patent_app_date] => 2009-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 7689 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0082/20100082948.pdf [firstpage_image] =>[orig_patent_app_number] => 12493951 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/493951
CHANNEL COMMAND WORD PRE-FETCHING APPARATUS Jun 28, 2009 Abandoned
Array ( [id] => 6362793 [patent_doc_number] => 20100332807 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-30 [patent_title] => 'PERFORMING ESCAPE ACTIONS IN TRANSACTIONS' [patent_app_type] => utility [patent_app_number] => 12/493167 [patent_app_country] => US [patent_app_date] => 2009-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6804 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0332/20100332807.pdf [firstpage_image] =>[orig_patent_app_number] => 12493167 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/493167
Performing escape actions in transactions Jun 25, 2009 Issued
Array ( [id] => 6362805 [patent_doc_number] => 20100332809 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-30 [patent_title] => 'Methods and Devices for Saving and/or Restoring a State of a Pattern-Recognition Processor' [patent_app_type] => utility [patent_app_number] => 12/492824 [patent_app_country] => US [patent_app_date] => 2009-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9061 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0332/20100332809.pdf [firstpage_image] =>[orig_patent_app_number] => 12492824 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/492824
Methods and devices for saving and/or restoring a state of a pattern-recognition processor Jun 25, 2009 Issued
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