
Michael Patrick Stafira
Examiner (ID: 6821, Phone: (571)272-2430 , Office: P/2886 )
| Most Active Art Unit | 2877 |
| Art Unit(s) | 2877, 2886, 3621, 2505 |
| Total Applications | 2900 |
| Issued Applications | 2466 |
| Pending Applications | 229 |
| Abandoned Applications | 230 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 20221500
[patent_doc_number] => 20250284431
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-09-11
[patent_title] => Data Processing Method and Apparatus
[patent_app_type] => utility
[patent_app_number] => 19/214267
[patent_app_country] => US
[patent_app_date] => 2025-05-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9873
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 49
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19214267
[rel_patent_id] =>[rel_patent_doc_number] =>) 19/214267 | Data Processing Method and Apparatus | May 20, 2025 | Pending |
Array
(
[id] => 20221593
[patent_doc_number] => 20250284524
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-09-11
[patent_title] => SYSTEM, APPARATUS AND METHOD FOR ACCESSING MULTIPLE ADDRESS SPACES VIA A VIRTUALIZATION DEVICE
[patent_app_type] => utility
[patent_app_number] => 19/213993
[patent_app_country] => US
[patent_app_date] => 2025-05-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3598
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 215
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19213993
[rel_patent_id] =>[rel_patent_doc_number] =>) 19/213993 | SYSTEM, APPARATUS AND METHOD FOR ACCESSING MULTIPLE ADDRESS SPACES VIA A VIRTUALIZATION DEVICE | May 19, 2025 | Pending |
Array
(
[id] => 20738412
[patent_doc_number] => 20260147714
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2026-05-28
[patent_title] => METHOD AND APPARATUS WITH DATA PRELOADING
[patent_app_type] => utility
[patent_app_number] => 19/202768
[patent_app_country] => US
[patent_app_date] => 2025-05-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3471
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19202768
[rel_patent_id] =>[rel_patent_doc_number] =>) 19/202768 | METHOD AND APPARATUS WITH DATA PRELOADING | May 7, 2025 | Pending |
Array
(
[id] => 20195545
[patent_doc_number] => 20250272255
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-08-28
[patent_title] => TECHNIQUES FOR COMMAND BUS TRAINING TO A MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 19/091628
[patent_app_country] => US
[patent_app_date] => 2025-03-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11819
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19091628
[rel_patent_id] =>[rel_patent_doc_number] =>) 19/091628 | TECHNIQUES FOR COMMAND BUS TRAINING TO A MEMORY DEVICE | Mar 25, 2025 | Pending |
Array
(
[id] => 20095147
[patent_doc_number] => 20250225083
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-07-10
[patent_title] => HYBRID VICTIM CACHE AND WRITE MISS BUFFER WITH FENCE OPERATION
[patent_app_type] => utility
[patent_app_number] => 19/071090
[patent_app_country] => US
[patent_app_date] => 2025-03-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 20938
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19071090
[rel_patent_id] =>[rel_patent_doc_number] =>) 19/071090 | HYBRID VICTIM CACHE AND WRITE MISS BUFFER WITH FENCE OPERATION | Mar 4, 2025 | Pending |
Array
(
[id] => 20043301
[patent_doc_number] => 20250181523
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-06-05
[patent_title] => METHOD AND SYSTEM FOR IMPROVING EFFICIENCY OF PROTECTING A MULTI-CONTENT PROCESS
[patent_app_type] => utility
[patent_app_number] => 19/047944
[patent_app_country] => US
[patent_app_date] => 2025-02-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2156
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 156
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19047944
[rel_patent_id] =>[rel_patent_doc_number] =>) 19/047944 | METHOD AND SYSTEM FOR IMPROVING EFFICIENCY OF PROTECTING A MULTI-CONTENT PROCESS | Feb 6, 2025 | Pending |
Array
(
[id] => 20043016
[patent_doc_number] => 20250181238
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-06-05
[patent_title] => MULTICORE, MULTIBANK, FULLY CONCURRENT COHERENCE CONTROLLER
[patent_app_type] => utility
[patent_app_number] => 19/047071
[patent_app_country] => US
[patent_app_date] => 2025-02-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 19483
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19047071
[rel_patent_id] =>[rel_patent_doc_number] =>) 19/047071 | MULTICORE, MULTIBANK, FULLY CONCURRENT COHERENCE CONTROLLER | Feb 5, 2025 | Pending |
Array
(
[id] => 20043271
[patent_doc_number] => 20250181493
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-06-05
[patent_title] => MULTI-PERIPHERAL AND/OR MULTI-FUNCTION EXPORT
[patent_app_type] => utility
[patent_app_number] => 19/038856
[patent_app_country] => US
[patent_app_date] => 2025-01-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6608
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19038856
[rel_patent_id] =>[rel_patent_doc_number] =>) 19/038856 | MULTI-PERIPHERAL AND/OR MULTI-FUNCTION EXPORT | Jan 27, 2025 | Pending |
Array
(
[id] => 20026942
[patent_doc_number] => 20250165164
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-05-22
[patent_title] => METHOD FOR OPERATING MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 19/029632
[patent_app_country] => US
[patent_app_date] => 2025-01-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6030
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19029632
[rel_patent_id] =>[rel_patent_doc_number] =>) 19/029632 | METHOD FOR OPERATING MEMORY DEVICE | Jan 16, 2025 | Pending |
Array
(
[id] => 20020614
[patent_doc_number] => 20250158836
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-05-15
[patent_title] => Storage of Data and Metadata in a Storage Network
[patent_app_type] => utility
[patent_app_number] => 19/024413
[patent_app_country] => US
[patent_app_date] => 2025-01-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 25085
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 132
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19024413
[rel_patent_id] =>[rel_patent_doc_number] =>) 19/024413 | Storage of Data and Metadata in a Storage Network | Jan 15, 2025 | Pending |
Array
(
[id] => 20428144
[patent_doc_number] => 20250390234
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-12-25
[patent_title] => UNIVERSAL FLASH STORAGE DEVICE AND SYSTEM AND OPERATION METHODS OF THE SAME
[patent_app_type] => utility
[patent_app_number] => 19/023056
[patent_app_country] => US
[patent_app_date] => 2025-01-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10574
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19023056
[rel_patent_id] =>[rel_patent_doc_number] =>) 19/023056 | UNIVERSAL FLASH STORAGE DEVICE AND SYSTEM AND OPERATION METHODS OF THE SAME | Jan 14, 2025 | Pending |
Array
(
[id] => 20009459
[patent_doc_number] => 20250147681
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-05-08
[patent_title] => On-Chip Atomic Transaction Engine
[patent_app_type] => utility
[patent_app_number] => 19/017209
[patent_app_country] => US
[patent_app_date] => 2025-01-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12365
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19017209
[rel_patent_id] =>[rel_patent_doc_number] =>) 19/017209 | On-Chip Atomic Transaction Engine | Jan 9, 2025 | Pending |
Array
(
[id] => 20124257
[patent_doc_number] => 20250239288
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-07-24
[patent_title] => Protocol For Refresh Between A Memory Controller And A Memory Device
[patent_app_type] => utility
[patent_app_number] => 18/991946
[patent_app_country] => US
[patent_app_date] => 2024-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 0
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18991946
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/991946 | Protocol For Refresh Between A Memory Controller And A Memory Device | Dec 22, 2024 | Pending |
Array
(
[id] => 20061730
[patent_doc_number] => 20250199952
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-06-19
[patent_title] => IN MEMORY COLD PAGES DETECTOR
[patent_app_type] => utility
[patent_app_number] => 18/970255
[patent_app_country] => US
[patent_app_date] => 2024-12-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5217
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18970255
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/970255 | IN MEMORY COLD PAGES DETECTOR | Dec 4, 2024 | Pending |
Array
(
[id] => 19834339
[patent_doc_number] => 20250086125
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-03-13
[patent_title] => NEURAL NETWORK ACCELERATOR WITH MEMORY HAVING BANK-SPECIFIC CLOCK DOMAIN CROSSING BUFFERS
[patent_app_type] => utility
[patent_app_number] => 18/954764
[patent_app_country] => US
[patent_app_date] => 2024-11-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 20031
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18954764
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/954764 | NEURAL NETWORK ACCELERATOR WITH MEMORY HAVING BANK-SPECIFIC CLOCK DOMAIN CROSSING BUFFERS | Nov 20, 2024 | Pending |
Array
(
[id] => 20709577
[patent_doc_number] => 20260133911
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2026-05-14
[patent_title] => ENHANCING METADATA STORAGE IN CACHES
[patent_app_type] => utility
[patent_app_number] => 18/945662
[patent_app_country] => US
[patent_app_date] => 2024-11-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4350
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18945662
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/945662 | Enhancing metadata storage in caches | Nov 12, 2024 | Issued |
Array
(
[id] => 20035047
[patent_doc_number] => 20250173269
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-05-29
[patent_title] => SYSTEMS, METHODS, AND APPARATUS FOR CACHING ON A STORAGE DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/926110
[patent_app_country] => US
[patent_app_date] => 2024-10-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7484
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 42
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18926110
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/926110 | SYSTEMS, METHODS, AND APPARATUS FOR CACHING ON A STORAGE DEVICE | Oct 23, 2024 | Pending |
Array
(
[id] => 20027161
[patent_doc_number] => 20250165383
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-05-22
[patent_title] => APPARATUSES, SYSTEMS, AND METHODS FOR DECODING METADATA POSITION DURING READ OPERATIONS
[patent_app_type] => utility
[patent_app_number] => 18/920337
[patent_app_country] => US
[patent_app_date] => 2024-10-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2608
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18920337
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/920337 | APPARATUSES, SYSTEMS, AND METHODS FOR DECODING METADATA POSITION DURING READ OPERATIONS | Oct 17, 2024 | Pending |
Array
(
[id] => 20351572
[patent_doc_number] => 20250348424
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-11-13
[patent_title] => MEMORY CONTROLLER FOR ENSURING WRITE PERFORMANCE, STORAGE APPARATUS HAVING THE SAME, AND OPERATION METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/912589
[patent_app_country] => US
[patent_app_date] => 2024-10-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 1173
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18912589
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/912589 | MEMORY CONTROLLER FOR ENSURING WRITE PERFORMANCE, STORAGE APPARATUS HAVING THE SAME, AND OPERATION METHOD THEREOF | Oct 10, 2024 | Pending |
Array
(
[id] => 19725894
[patent_doc_number] => 20250028645
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-01-23
[patent_title] => METHODS AND APPARATUS FOR INFLIGHT DATA FORWARDING AND INVALIDATION OF PENDING WRITES IN STORE QUEUE
[patent_app_type] => utility
[patent_app_number] => 18/907746
[patent_app_country] => US
[patent_app_date] => 2024-10-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 95400
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18907746
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/907746 | Methods and apparatus for inflight data forwarding and invalidation of pending writes in store queue | Oct 6, 2024 | Issued |