Search

Michael Patrick Stafira

Examiner (ID: 7840, Phone: (571)272-2430 , Office: P/2886 )

Most Active Art Unit
2877
Art Unit(s)
2505, 2877, 3621, 2886
Total Applications
2739
Issued Applications
2325
Pending Applications
209
Abandoned Applications
205

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1192679 [patent_doc_number] => 06735732 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-05-11 [patent_title] => 'Clock adjusting method and circuit device' [patent_app_type] => B2 [patent_app_number] => 10/460393 [patent_app_country] => US [patent_app_date] => 2003-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6489 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/735/06735732.pdf [firstpage_image] =>[orig_patent_app_number] => 10460393 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/460393
Clock adjusting method and circuit device Jun 12, 2003 Issued
09/762517 INTEGRATED CIRCUIT WITH AN INTEGRATED MODULE TEST Jun 6, 2001 Abandoned
Array ( [id] => 6881039 [patent_doc_number] => 20010032327 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-18 [patent_title] => 'System and method of processing memory' [patent_app_type] => new [patent_app_number] => 09/821326 [patent_app_country] => US [patent_app_date] => 2001-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 11489 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0032/20010032327.pdf [firstpage_image] =>[orig_patent_app_number] => 09821326 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/821326
System and method of processing memory Mar 28, 2001 Issued
Array ( [id] => 5910675 [patent_doc_number] => 20020144210 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-03 [patent_title] => 'SDRAM address error detection method and apparatus' [patent_app_type] => new [patent_app_number] => 09/820436 [patent_app_country] => US [patent_app_date] => 2001-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3555 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0144/20020144210.pdf [firstpage_image] =>[orig_patent_app_number] => 09820436 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/820436
SDRAM address error detection method and apparatus Mar 28, 2001 Issued
Array ( [id] => 6896761 [patent_doc_number] => 20010027551 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-04 [patent_title] => 'CD-ROM decoder' [patent_app_type] => new [patent_app_number] => 09/818149 [patent_app_country] => US [patent_app_date] => 2001-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6368 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0027/20010027551.pdf [firstpage_image] =>[orig_patent_app_number] => 09818149 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/818149
CD-ROM decoder Mar 26, 2001 Abandoned
Array ( [id] => 6896762 [patent_doc_number] => 20010027552 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-04 [patent_title] => 'CD-ROM decoder' [patent_app_type] => new [patent_app_number] => 09/818051 [patent_app_country] => US [patent_app_date] => 2001-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4440 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0027/20010027552.pdf [firstpage_image] =>[orig_patent_app_number] => 09818051 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/818051
CD-ROM decoder Mar 26, 2001 Abandoned
Array ( [id] => 6426405 [patent_doc_number] => 20020184598 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-05 [patent_title] => 'Providing a header checksum for packet data communications' [patent_app_type] => new [patent_app_number] => 09/819523 [patent_app_country] => US [patent_app_date] => 2001-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2502 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0184/20020184598.pdf [firstpage_image] =>[orig_patent_app_number] => 09819523 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/819523
Providing a header checksum for packet data communications Mar 26, 2001 Issued
Array ( [id] => 6562528 [patent_doc_number] => 20020138793 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-26 [patent_title] => 'Iterative decoding of differentially modulated symbols' [patent_app_type] => new [patent_app_number] => 09/818307 [patent_app_country] => US [patent_app_date] => 2001-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3813 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20020138793.pdf [firstpage_image] =>[orig_patent_app_number] => 09818307 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/818307
Iterative decoding of differentially modulated symbols Mar 25, 2001 Abandoned
Array ( [id] => 1186459 [patent_doc_number] => 06742148 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-25 [patent_title] => 'System and method for testing memory while an operating system is active' [patent_app_type] => B1 [patent_app_number] => 09/800119 [patent_app_country] => US [patent_app_date] => 2001-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3047 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/742/06742148.pdf [firstpage_image] =>[orig_patent_app_number] => 09800119 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/800119
System and method for testing memory while an operating system is active Mar 4, 2001 Issued
Array ( [id] => 6888681 [patent_doc_number] => 20010024136 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-09-27 [patent_title] => 'Semiconductor integrated circuit compensating variations of delay time' [patent_app_type] => new [patent_app_number] => 09/767945 [patent_app_country] => US [patent_app_date] => 2001-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6625 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0024/20010024136.pdf [firstpage_image] =>[orig_patent_app_number] => 09767945 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/767945
Semiconductor integrated circuit compensating variations of delay time Jan 23, 2001 Issued
Array ( [id] => 6962925 [patent_doc_number] => 20010013108 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-09 [patent_title] => 'Error indication independent of data format' [patent_app_type] => new [patent_app_number] => 09/767638 [patent_app_country] => US [patent_app_date] => 2001-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1784 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20010013108.pdf [firstpage_image] =>[orig_patent_app_number] => 09767638 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/767638
Error indication independent of data format Jan 22, 2001 Abandoned
Array ( [id] => 6935545 [patent_doc_number] => 20010056567 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-27 [patent_title] => 'Address parity error processing method, and apparatus and storage for the method' [patent_app_type] => new [patent_app_number] => 09/765422 [patent_app_country] => US [patent_app_date] => 2001-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9287 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0056/20010056567.pdf [firstpage_image] =>[orig_patent_app_number] => 09765422 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/765422
Address parity error processing method, and apparatus and storage for the method Jan 21, 2001 Issued
Array ( [id] => 6484645 [patent_doc_number] => 20020023248 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-21 [patent_title] => 'Medium defect detection method and data storage apparatus' [patent_app_type] => new [patent_app_number] => 09/764385 [patent_app_country] => US [patent_app_date] => 2001-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9576 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20020023248.pdf [firstpage_image] =>[orig_patent_app_number] => 09764385 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/764385
Medium defect detection method and data storage apparatus Jan 18, 2001 Abandoned
Array ( [id] => 1292297 [patent_doc_number] => 06643809 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-11-04 [patent_title] => 'Semiconductor device and semiconductor device testing method' [patent_app_type] => B2 [patent_app_number] => 09/764415 [patent_app_country] => US [patent_app_date] => 2001-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4647 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/643/06643809.pdf [firstpage_image] =>[orig_patent_app_number] => 09764415 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/764415
Semiconductor device and semiconductor device testing method Jan 18, 2001 Issued
Array ( [id] => 6900411 [patent_doc_number] => 20010010087 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-07-26 [patent_title] => 'Method of analyzing fault occurring in semiconductor device' [patent_app_type] => new [patent_app_number] => 09/764453 [patent_app_country] => US [patent_app_date] => 2001-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3803 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0010/20010010087.pdf [firstpage_image] =>[orig_patent_app_number] => 09764453 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/764453
Method of analyzing fault occurring in semiconductor device Jan 18, 2001 Abandoned
Array ( [id] => 5874019 [patent_doc_number] => 20020048856 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-25 [patent_title] => 'Method of testing a semiconductor memory device' [patent_app_type] => new [patent_app_number] => 09/761847 [patent_app_country] => US [patent_app_date] => 2001-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 14093 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0048/20020048856.pdf [firstpage_image] =>[orig_patent_app_number] => 09761847 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/761847
Method of testing a semiconductor memory device Jan 17, 2001 Issued
Array ( [id] => 1240991 [patent_doc_number] => 06691273 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-02-10 [patent_title] => 'Error correction using packet combining during soft handover' [patent_app_type] => B2 [patent_app_number] => 09/764506 [patent_app_country] => US [patent_app_date] => 2001-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2129 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/691/06691273.pdf [firstpage_image] =>[orig_patent_app_number] => 09764506 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/764506
Error correction using packet combining during soft handover Jan 16, 2001 Issued
Array ( [id] => 7016220 [patent_doc_number] => 20010052097 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-13 [patent_title] => 'Method and apparatus for testing semiconductor devices' [patent_app_type] => new [patent_app_number] => 09/761199 [patent_app_country] => US [patent_app_date] => 2001-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 9641 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20010052097.pdf [firstpage_image] =>[orig_patent_app_number] => 09761199 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/761199
Method and apparatus for testing semiconductor devices Jan 15, 2001 Issued
Array ( [id] => 6310869 [patent_doc_number] => 20020095631 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-18 [patent_title] => 'Input/output continuity test mode circuit' [patent_app_type] => new [patent_app_number] => 09/764169 [patent_app_country] => US [patent_app_date] => 2001-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2190 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20020095631.pdf [firstpage_image] =>[orig_patent_app_number] => 09764169 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/764169
Input/output continuity test mode circuit Jan 15, 2001 Issued
Array ( [id] => 1396515 [patent_doc_number] => 06567949 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-05-20 [patent_title] => 'Method and configuration for error masking' [patent_app_type] => B2 [patent_app_number] => 09/725347 [patent_app_country] => US [patent_app_date] => 2000-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4603 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/567/06567949.pdf [firstpage_image] =>[orig_patent_app_number] => 09725347 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/725347
Method and configuration for error masking Nov 28, 2000 Issued
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