Search

Michael R. Fleming

Examiner (ID: 18906)

Most Active Art Unit
2306
Art Unit(s)
2308, 2306
Total Applications
577
Issued Applications
543
Pending Applications
0
Abandoned Applications
34

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2347037 [patent_doc_number] => 04713812 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-12-15 [patent_title] => 'Method and apparatus for replacement of data and of a data memory in an automotive-type electronic control system' [patent_app_type] => 1 [patent_app_number] => 6/838176 [patent_app_country] => US [patent_app_date] => 1986-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1817 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/713/04713812.pdf [firstpage_image] =>[orig_patent_app_number] => 838176 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/838176
Method and apparatus for replacement of data and of a data memory in an automotive-type electronic control system Mar 9, 1986 Issued
Array ( [id] => 2333316 [patent_doc_number] => 04698812 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-10-06 [patent_title] => 'Memory system employing a zero DC power gate array for error correction' [patent_app_type] => 1 [patent_app_number] => 6/835776 [patent_app_country] => US [patent_app_date] => 1986-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4405 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/698/04698812.pdf [firstpage_image] =>[orig_patent_app_number] => 835776 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/835776
Memory system employing a zero DC power gate array for error correction Mar 2, 1986 Issued
Array ( [id] => 2422438 [patent_doc_number] => 04719627 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-01-12 [patent_title] => 'Memory system employing a low DC power gate array for error correction' [patent_app_type] => 1 [patent_app_number] => 6/835777 [patent_app_country] => US [patent_app_date] => 1986-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4398 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/719/04719627.pdf [firstpage_image] =>[orig_patent_app_number] => 835777 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/835777
Memory system employing a low DC power gate array for error correction Mar 2, 1986 Issued
Array ( [id] => 2490593 [patent_doc_number] => 04823279 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-04-18 [patent_title] => 'Coordinate conversion system and method for controlling an industrial robot' [patent_app_type] => 1 [patent_app_number] => 6/834204 [patent_app_country] => US [patent_app_date] => 1986-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 11015 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 325 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/823/04823279.pdf [firstpage_image] =>[orig_patent_app_number] => 834204 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/834204
Coordinate conversion system and method for controlling an industrial robot Feb 26, 1986 Issued
Array ( [id] => 2567510 [patent_doc_number] => 04817039 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-03-28 [patent_title] => 'Atmospheric controlled video simulation system' [patent_app_type] => 1 [patent_app_number] => 6/833158 [patent_app_country] => US [patent_app_date] => 1986-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2604 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/817/04817039.pdf [firstpage_image] =>[orig_patent_app_number] => 833158 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/833158
Atmospheric controlled video simulation system Feb 26, 1986 Issued
Array ( [id] => 2347101 [patent_doc_number] => 04713816 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-12-15 [patent_title] => 'Three module memory system constructed with symbol-wide memory chips and having an error protection feature, each symbol consisting of 2I+1 bits' [patent_app_type] => 1 [patent_app_number] => 6/833644 [patent_app_country] => US [patent_app_date] => 1986-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 20 [patent_no_of_words] => 4593 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/713/04713816.pdf [firstpage_image] =>[orig_patent_app_number] => 833644 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/833644
Three module memory system constructed with symbol-wide memory chips and having an error protection feature, each symbol consisting of 2I+1 bits Feb 24, 1986 Issued
Array ( [id] => 2230331 [patent_doc_number] => 04625312 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-11-25 [patent_title] => 'Test and maintenance method and apparatus for investigation of intermittent faults in a data processing system' [patent_app_type] => 1 [patent_app_number] => 6/830903 [patent_app_country] => US [patent_app_date] => 1986-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 6451 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/625/04625312.pdf [firstpage_image] =>[orig_patent_app_number] => 830903 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/830903
Test and maintenance method and apparatus for investigation of intermittent faults in a data processing system Feb 17, 1986 Issued
Array ( [id] => 2424040 [patent_doc_number] => 04736377 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-04-05 [patent_title] => 'Method for determining reliability of high speed digital transmission by use of a synchronized low speed side channel' [patent_app_type] => 1 [patent_app_number] => 6/828184 [patent_app_country] => US [patent_app_date] => 1986-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 10101 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/736/04736377.pdf [firstpage_image] =>[orig_patent_app_number] => 828184 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/828184
Method for determining reliability of high speed digital transmission by use of a synchronized low speed side channel Feb 10, 1986 Issued
Array ( [id] => 2322333 [patent_doc_number] => 04716567 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-12-29 [patent_title] => 'Method of transmitting digital data in which error detection codes are dispersed using alternate delay times' [patent_app_type] => 1 [patent_app_number] => 6/827606 [patent_app_country] => US [patent_app_date] => 1986-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 23 [patent_no_of_words] => 5694 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/716/04716567.pdf [firstpage_image] =>[orig_patent_app_number] => 827606 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/827606
Method of transmitting digital data in which error detection codes are dispersed using alternate delay times Feb 9, 1986 Issued
Array ( [id] => 2396332 [patent_doc_number] => 04777598 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-10-11 [patent_title] => 'Image processing systems and methods' [patent_app_type] => 1 [patent_app_number] => 6/827240 [patent_app_country] => US [patent_app_date] => 1986-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 4212 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/777/04777598.pdf [firstpage_image] =>[orig_patent_app_number] => 827240 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/827240
Image processing systems and methods Feb 6, 1986 Issued
Array ( [id] => 2451743 [patent_doc_number] => 04722085 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-01-26 [patent_title] => 'High capacity disk storage system having unusually high fault tolerance level and bandpass' [patent_app_type] => 1 [patent_app_number] => 6/825174 [patent_app_country] => US [patent_app_date] => 1986-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3010 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/722/04722085.pdf [firstpage_image] =>[orig_patent_app_number] => 825174 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/825174
High capacity disk storage system having unusually high fault tolerance level and bandpass Feb 2, 1986 Issued
06/825495 METHOD OF PROVIDING A HIGH CAPACITY DISK STORAGE SYSTEM HAVING UNUSUALLY HIGH FAULT TOLERANCE LEVEL AND BANDPASS Feb 2, 1986 Abandoned
Array ( [id] => 2298988 [patent_doc_number] => 04710932 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-12-01 [patent_title] => 'Method of and apparatus for fault detection in digital circuits by comparison of test signals applied to a test circuit and a faultless reference circuit' [patent_app_type] => 1 [patent_app_number] => 6/819225 [patent_app_country] => US [patent_app_date] => 1986-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3451 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/710/04710932.pdf [firstpage_image] =>[orig_patent_app_number] => 819225 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/819225
Method of and apparatus for fault detection in digital circuits by comparison of test signals applied to a test circuit and a faultless reference circuit Jan 14, 1986 Issued
Array ( [id] => 2341071 [patent_doc_number] => 04701923 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-10-20 [patent_title] => 'Adaptively coded data communication system with half duplex and/or full duplex function' [patent_app_type] => 1 [patent_app_number] => 6/818825 [patent_app_country] => US [patent_app_date] => 1986-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5342 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/701/04701923.pdf [firstpage_image] =>[orig_patent_app_number] => 818825 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/818825
Adaptively coded data communication system with half duplex and/or full duplex function Jan 13, 1986 Issued
Array ( [id] => 2298902 [patent_doc_number] => 04710926 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-12-01 [patent_title] => 'Fault recovery in a distributed processing system' [patent_app_type] => 1 [patent_app_number] => 6/814115 [patent_app_country] => US [patent_app_date] => 1985-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 33 [patent_no_of_words] => 7813 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/710/04710926.pdf [firstpage_image] =>[orig_patent_app_number] => 814115 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/814115
Fault recovery in a distributed processing system Dec 26, 1985 Issued
Array ( [id] => 2341665 [patent_doc_number] => 04712217 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-12-08 [patent_title] => 'System for transmitting digital information and maintaining a minimum paulse density' [patent_app_type] => 1 [patent_app_number] => 6/811914 [patent_app_country] => US [patent_app_date] => 1985-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 7039 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/712/04712217.pdf [firstpage_image] =>[orig_patent_app_number] => 811914 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/811914
System for transmitting digital information and maintaining a minimum paulse density Dec 19, 1985 Issued
Array ( [id] => 2361377 [patent_doc_number] => 04688222 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-08-18 [patent_title] => 'Built-in parallel testing circuit for use in a processor' [patent_app_type] => 1 [patent_app_number] => 6/810105 [patent_app_country] => US [patent_app_date] => 1985-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 5712 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/688/04688222.pdf [firstpage_image] =>[orig_patent_app_number] => 810105 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/810105
Built-in parallel testing circuit for use in a processor Dec 16, 1985 Issued
Array ( [id] => 2333235 [patent_doc_number] => 04698808 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-10-06 [patent_title] => 'Method for detecting intermittent error in volatile memory' [patent_app_type] => 1 [patent_app_number] => 6/806076 [patent_app_country] => US [patent_app_date] => 1985-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1617 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/698/04698808.pdf [firstpage_image] =>[orig_patent_app_number] => 806076 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/806076
Method for detecting intermittent error in volatile memory Dec 4, 1985 Issued
Array ( [id] => 2390512 [patent_doc_number] => 04720830 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-01-19 [patent_title] => 'CRC calculation apparatus having reduced output bus size' [patent_app_type] => 1 [patent_app_number] => 6/803351 [patent_app_country] => US [patent_app_date] => 1985-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 25 [patent_no_of_words] => 11444 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/720/04720830.pdf [firstpage_image] =>[orig_patent_app_number] => 803351 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/803351
CRC calculation apparatus having reduced output bus size Dec 1, 1985 Issued
Array ( [id] => 2456608 [patent_doc_number] => 04723243 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-02-02 [patent_title] => 'CRC calculation machine with variable bit boundary' [patent_app_type] => 1 [patent_app_number] => 6/803466 [patent_app_country] => US [patent_app_date] => 1985-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 21 [patent_no_of_words] => 11644 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/723/04723243.pdf [firstpage_image] =>[orig_patent_app_number] => 803466 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/803466
CRC calculation machine with variable bit boundary Dec 1, 1985 Issued
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