
Michael R. Fleming
Examiner (ID: 18906)
| Most Active Art Unit | 2306 |
| Art Unit(s) | 2308, 2306 |
| Total Applications | 577 |
| Issued Applications | 543 |
| Pending Applications | 0 |
| Abandoned Applications | 34 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
| 07/225504 | FINDING FAULTS IN CIRCUIT BOARDS | Jul 27, 1988 | Abandoned |
Array
(
[id] => 2483781
[patent_doc_number] => 04872112
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-10-03
[patent_title] => 'Recipe calculator'
[patent_app_type] => 1
[patent_app_number] => 7/223957
[patent_app_country] => US
[patent_app_date] => 1988-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 1777
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 12
[patent_words_short_claim] => 19
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/872/04872112.pdf
[firstpage_image] =>[orig_patent_app_number] => 223957
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/223957 | Recipe calculator | Jul 24, 1988 | Issued |
Array
(
[id] => 2624509
[patent_doc_number] => 04943965
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-07-24
[patent_title] => 'Digital signal decoding method and circuit therefor'
[patent_app_type] => 1
[patent_app_number] => 7/217585
[patent_app_country] => US
[patent_app_date] => 1988-07-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3022
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 160
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/943/04943965.pdf
[firstpage_image] =>[orig_patent_app_number] => 217585
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/217585 | Digital signal decoding method and circuit therefor | Jul 10, 1988 | Issued |
Array
(
[id] => 2634490
[patent_doc_number] => 04920537
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-04-24
[patent_title] => 'Method and apparatus for non-intrusive bit error rate testing'
[patent_app_type] => 1
[patent_app_number] => 7/215394
[patent_app_country] => US
[patent_app_date] => 1988-07-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2767
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 279
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/920/04920537.pdf
[firstpage_image] =>[orig_patent_app_number] => 215394
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/215394 | Method and apparatus for non-intrusive bit error rate testing | Jul 4, 1988 | Issued |
Array
(
[id] => 2566877
[patent_doc_number] => 04942578
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-07-17
[patent_title] => 'Buffer control method and apparatus'
[patent_app_type] => 1
[patent_app_number] => 7/215036
[patent_app_country] => US
[patent_app_date] => 1988-07-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 2619
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/942/04942578.pdf
[firstpage_image] =>[orig_patent_app_number] => 215036
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/215036 | Buffer control method and apparatus | Jul 4, 1988 | Issued |
Array
(
[id] => 2647875
[patent_doc_number] => 04914656
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-04-03
[patent_title] => 'Disk drive memory'
[patent_app_type] => 1
[patent_app_number] => 7/212434
[patent_app_country] => US
[patent_app_date] => 1988-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 7628
[patent_no_of_claims] => 64
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/914/04914656.pdf
[firstpage_image] =>[orig_patent_app_number] => 212434
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/212434 | Disk drive memory | Jun 27, 1988 | Issued |
Array
(
[id] => 2665904
[patent_doc_number] => 04930128
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-05-29
[patent_title] => 'Method for restart of online computer system and apparatus for carrying out the same'
[patent_app_type] => 1
[patent_app_number] => 7/211045
[patent_app_country] => US
[patent_app_date] => 1988-06-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 3012
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 186
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/930/04930128.pdf
[firstpage_image] =>[orig_patent_app_number] => 211045
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/211045 | Method for restart of online computer system and apparatus for carrying out the same | Jun 23, 1988 | Issued |
Array
(
[id] => 2612934
[patent_doc_number] => 04932028
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-06-05
[patent_title] => 'Error log system for self-testing in very large scale integrated circuit (VLSI) units'
[patent_app_type] => 1
[patent_app_number] => 7/209664
[patent_app_country] => US
[patent_app_date] => 1988-06-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 24
[patent_no_of_words] => 7909
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 69
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/932/04932028.pdf
[firstpage_image] =>[orig_patent_app_number] => 209664
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/209664 | Error log system for self-testing in very large scale integrated circuit (VLSI) units | Jun 20, 1988 | Issued |
Array
(
[id] => 2634528
[patent_doc_number] => 04920539
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-04-24
[patent_title] => 'Memory error correction system'
[patent_app_type] => 1
[patent_app_number] => 7/209285
[patent_app_country] => US
[patent_app_date] => 1988-06-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 4321
[patent_no_of_claims] => 42
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/920/04920539.pdf
[firstpage_image] =>[orig_patent_app_number] => 209285
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/209285 | Memory error correction system | Jun 19, 1988 | Issued |
Array
(
[id] => 2566818
[patent_doc_number] => 04942575
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-07-17
[patent_title] => 'Error connection device for parity protected memory systems'
[patent_app_type] => 1
[patent_app_number] => 7/207874
[patent_app_country] => US
[patent_app_date] => 1988-06-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 2131
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/942/04942575.pdf
[firstpage_image] =>[orig_patent_app_number] => 207874
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/207874 | Error connection device for parity protected memory systems | Jun 16, 1988 | Issued |
Array
(
[id] => 2533394
[patent_doc_number] => 04873689
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-10-10
[patent_title] => 'Method and apparatus for collecting errors in the digital data of a television signal'
[patent_app_type] => 1
[patent_app_number] => 7/203405
[patent_app_country] => US
[patent_app_date] => 1988-06-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 5
[patent_no_of_words] => 5035
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 356
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/873/04873689.pdf
[firstpage_image] =>[orig_patent_app_number] => 203405
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/203405 | Method and apparatus for collecting errors in the digital data of a television signal | Jun 5, 1988 | Issued |
Array
(
[id] => 2633348
[patent_doc_number] => 04920476
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-04-24
[patent_title] => 'Electronic control for lighting panelboards'
[patent_app_type] => 1
[patent_app_number] => 7/199488
[patent_app_country] => US
[patent_app_date] => 1988-05-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 1411
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 144
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/920/04920476.pdf
[firstpage_image] =>[orig_patent_app_number] => 199488
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/199488 | Electronic control for lighting panelboards | May 26, 1988 | Issued |
Array
(
[id] => 2608988
[patent_doc_number] => 04922494
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-05-01
[patent_title] => 'Method of and circuit for decoding block-coded messages affected by symbol substitutions, insertions and deletions'
[patent_app_type] => 1
[patent_app_number] => 7/191206
[patent_app_country] => US
[patent_app_date] => 1988-05-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 5116
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 209
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/922/04922494.pdf
[firstpage_image] =>[orig_patent_app_number] => 191206
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/191206 | Method of and circuit for decoding block-coded messages affected by symbol substitutions, insertions and deletions | May 5, 1988 | Issued |
Array
(
[id] => 2638536
[patent_doc_number] => 04907231
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-03-06
[patent_title] => 'Memory cartridge-connectable electronic device such as electronic still video camera'
[patent_app_type] => 1
[patent_app_number] => 7/191064
[patent_app_country] => US
[patent_app_date] => 1988-05-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 9208
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 173
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/907/04907231.pdf
[firstpage_image] =>[orig_patent_app_number] => 191064
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/191064 | Memory cartridge-connectable electronic device such as electronic still video camera | May 5, 1988 | Issued |
Array
(
[id] => 2640019
[patent_doc_number] => 04916696
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-04-10
[patent_title] => 'Logic operation device'
[patent_app_type] => 1
[patent_app_number] => 7/188375
[patent_app_country] => US
[patent_app_date] => 1988-04-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3151
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/916/04916696.pdf
[firstpage_image] =>[orig_patent_app_number] => 188375
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/188375 | Logic operation device | Apr 28, 1988 | Issued |
Array
(
[id] => 2525475
[patent_doc_number] => 04852102
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-07-25
[patent_title] => 'Interleave sequence method'
[patent_app_type] => 1
[patent_app_number] => 7/187315
[patent_app_country] => US
[patent_app_date] => 1988-04-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 14
[patent_no_of_words] => 3112
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 244
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/852/04852102.pdf
[firstpage_image] =>[orig_patent_app_number] => 187315
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/187315 | Interleave sequence method | Apr 27, 1988 | Issued |
Array
(
[id] => 2638554
[patent_doc_number] => 04907232
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-03-06
[patent_title] => 'Fault-tolerant parallel processing system'
[patent_app_type] => 1
[patent_app_number] => 7/187474
[patent_app_country] => US
[patent_app_date] => 1988-04-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 4388
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 212
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/907/04907232.pdf
[firstpage_image] =>[orig_patent_app_number] => 187474
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/187474 | Fault-tolerant parallel processing system | Apr 27, 1988 | Issued |
Array
(
[id] => 2644115
[patent_doc_number] => 04893311
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-01-09
[patent_title] => 'CMOS implementation of a built-in self test input generator (BISTIG)'
[patent_app_type] => 1
[patent_app_number] => 7/185610
[patent_app_country] => US
[patent_app_date] => 1988-04-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 1581
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 390
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/893/04893311.pdf
[firstpage_image] =>[orig_patent_app_number] => 185610
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/185610 | CMOS implementation of a built-in self test input generator (BISTIG) | Apr 24, 1988 | Issued |
Array
(
[id] => 2629175
[patent_doc_number] => 04894829
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-01-16
[patent_title] => 'Comprehensive design and maintenance environment for test program sets'
[patent_app_type] => 1
[patent_app_number] => 7/184536
[patent_app_country] => US
[patent_app_date] => 1988-04-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 9
[patent_no_of_words] => 3941
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 329
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/894/04894829.pdf
[firstpage_image] =>[orig_patent_app_number] => 184536
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/184536 | Comprehensive design and maintenance environment for test program sets | Apr 20, 1988 | Issued |
Array
(
[id] => 2579625
[patent_doc_number] => 04901318
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-02-13
[patent_title] => 'Address generating circuit'
[patent_app_type] => 1
[patent_app_number] => 7/184335
[patent_app_country] => US
[patent_app_date] => 1988-04-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 17
[patent_no_of_words] => 5020
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 176
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/901/04901318.pdf
[firstpage_image] =>[orig_patent_app_number] => 184335
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/184335 | Address generating circuit | Apr 20, 1988 | Issued |