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Michael R. Fleming

Examiner (ID: 18906)

Most Active Art Unit
2306
Art Unit(s)
2308, 2306
Total Applications
577
Issued Applications
543
Pending Applications
0
Abandoned Applications
34

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2531564 [patent_doc_number] => 04881229 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-11-14 [patent_title] => 'Test circuit arrangement for a communication network and test method using same' [patent_app_type] => 1 [patent_app_number] => 7/111935 [patent_app_country] => US [patent_app_date] => 1987-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1990 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/881/04881229.pdf [firstpage_image] =>[orig_patent_app_number] => 111935 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/111935
Test circuit arrangement for a communication network and test method using same Oct 20, 1987 Issued
Array ( [id] => 2487020 [patent_doc_number] => 04876686 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-10-24 [patent_title] => 'Fault detection signal transmission system' [patent_app_type] => 1 [patent_app_number] => 7/110316 [patent_app_country] => US [patent_app_date] => 1987-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2101 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/876/04876686.pdf [firstpage_image] =>[orig_patent_app_number] => 110316 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/110316
Fault detection signal transmission system Oct 19, 1987 Issued
Array ( [id] => 2501527 [patent_doc_number] => 04860289 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-08-22 [patent_title] => 'Reset circuit for electrically isolated circuits communicating via uart' [patent_app_type] => 1 [patent_app_number] => 7/110354 [patent_app_country] => US [patent_app_date] => 1987-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 6338 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/860/04860289.pdf [firstpage_image] =>[orig_patent_app_number] => 110354 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/110354
Reset circuit for electrically isolated circuits communicating via uart Oct 18, 1987 Issued
Array ( [id] => 2527454 [patent_doc_number] => 04864501 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-09-05 [patent_title] => 'Word annotation system' [patent_app_type] => 1 [patent_app_number] => 7/106224 [patent_app_country] => US [patent_app_date] => 1987-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 15232 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/864/04864501.pdf [firstpage_image] =>[orig_patent_app_number] => 106224 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/106224
Word annotation system Oct 6, 1987 Issued
Array ( [id] => 2527471 [patent_doc_number] => 04864502 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-09-05 [patent_title] => 'Sentence analyzer' [patent_app_type] => 1 [patent_app_number] => 7/106535 [patent_app_country] => US [patent_app_date] => 1987-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 18 [patent_no_of_words] => 20883 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/864/04864502.pdf [firstpage_image] =>[orig_patent_app_number] => 106535 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/106535
Sentence analyzer Oct 6, 1987 Issued
Array ( [id] => 2498158 [patent_doc_number] => 04868750 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-09-19 [patent_title] => 'Collocational grammar system' [patent_app_type] => 1 [patent_app_number] => 7/106127 [patent_app_country] => US [patent_app_date] => 1987-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 19190 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/868/04868750.pdf [firstpage_image] =>[orig_patent_app_number] => 106127 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/106127
Collocational grammar system Oct 6, 1987 Issued
Array ( [id] => 2573327 [patent_doc_number] => 04849973 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-07-18 [patent_title] => 'Test system for random access memory' [patent_app_type] => 1 [patent_app_number] => 7/098144 [patent_app_country] => US [patent_app_date] => 1987-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3015 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/849/04849973.pdf [firstpage_image] =>[orig_patent_app_number] => 098144 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/098144
Test system for random access memory Sep 17, 1987 Issued
Array ( [id] => 2638441 [patent_doc_number] => 04907228 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-03-06 [patent_title] => 'Dual-rail processor with error checking at single rail interfaces' [patent_app_type] => 1 [patent_app_number] => 7/093584 [patent_app_country] => US [patent_app_date] => 1987-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 53 [patent_figures_cnt] => 56 [patent_no_of_words] => 20174 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/907/04907228.pdf [firstpage_image] =>[orig_patent_app_number] => 093584 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/093584
Dual-rail processor with error checking at single rail interfaces Sep 3, 1987 Issued
Array ( [id] => 2499645 [patent_doc_number] => 04868827 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-09-19 [patent_title] => 'Digital data processing system' [patent_app_type] => 1 [patent_app_number] => 7/089554 [patent_app_country] => US [patent_app_date] => 1987-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 6393 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 331 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/868/04868827.pdf [firstpage_image] =>[orig_patent_app_number] => 089554 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/089554
Digital data processing system Aug 25, 1987 Issued
Array ( [id] => 2487648 [patent_doc_number] => 04882731 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-11-21 [patent_title] => 'Data processing device composed of four data processing modules of identical construction, with protection both against simultaneous single-bit failures in the data processing modules and against failure of a single data processing module' [patent_app_type] => 1 [patent_app_number] => 7/087185 [patent_app_country] => US [patent_app_date] => 1987-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 5406 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 387 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/882/04882731.pdf [firstpage_image] =>[orig_patent_app_number] => 087185 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/087185
Data processing device composed of four data processing modules of identical construction, with protection both against simultaneous single-bit failures in the data processing modules and against failure of a single data processing module Aug 18, 1987 Issued
Array ( [id] => 2499702 [patent_doc_number] => 04868830 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-09-19 [patent_title] => 'Method and apparatus for implementing a traceback maximum-likelihood decoder in a hypercube network' [patent_app_type] => 1 [patent_app_number] => 7/086710 [patent_app_country] => US [patent_app_date] => 1987-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 3308 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/868/04868830.pdf [firstpage_image] =>[orig_patent_app_number] => 086710 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/086710
Method and apparatus for implementing a traceback maximum-likelihood decoder in a hypercube network Aug 17, 1987 Issued
Array ( [id] => 2501583 [patent_doc_number] => 04860292 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-08-22 [patent_title] => 'Communication protocol' [patent_app_type] => 1 [patent_app_number] => 7/085096 [patent_app_country] => US [patent_app_date] => 1987-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 22 [patent_no_of_words] => 9581 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/860/04860292.pdf [firstpage_image] =>[orig_patent_app_number] => 085096 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/085096
Communication protocol Aug 12, 1987 Issued
Array ( [id] => 2538493 [patent_doc_number] => 04839809 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-06-13 [patent_title] => 'Magnetic personal turning monitor' [patent_app_type] => 1 [patent_app_number] => 7/083947 [patent_app_country] => US [patent_app_date] => 1987-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 1997 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/839/04839809.pdf [firstpage_image] =>[orig_patent_app_number] => 083947 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/083947
Magnetic personal turning monitor Aug 3, 1987 Issued
Array ( [id] => 2528980 [patent_doc_number] => 04864579 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-09-05 [patent_title] => 'Semiconductor integrated circuit device' [patent_app_type] => 1 [patent_app_number] => 7/081094 [patent_app_country] => US [patent_app_date] => 1987-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 6017 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 369 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/864/04864579.pdf [firstpage_image] =>[orig_patent_app_number] => 081094 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/081094
Semiconductor integrated circuit device Aug 2, 1987 Issued
Array ( [id] => 2496271 [patent_doc_number] => 04821271 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-04-11 [patent_title] => 'Methods and circuits for checking integrated circuit chips having programmable outputs' [patent_app_type] => 1 [patent_app_number] => 7/079444 [patent_app_country] => US [patent_app_date] => 1987-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1925 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 288 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/821/04821271.pdf [firstpage_image] =>[orig_patent_app_number] => 079444 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/079444
Methods and circuits for checking integrated circuit chips having programmable outputs Jul 29, 1987 Issued
Array ( [id] => 2525383 [patent_doc_number] => 04852097 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-07-25 [patent_title] => 'Method for forming data block protection information for serial data bit sequences by means of cyclical binary codes' [patent_app_type] => 1 [patent_app_number] => 7/076002 [patent_app_country] => US [patent_app_date] => 1987-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 3727 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/852/04852097.pdf [firstpage_image] =>[orig_patent_app_number] => 076002 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/076002
Method for forming data block protection information for serial data bit sequences by means of cyclical binary codes Jul 20, 1987 Issued
Array ( [id] => 2573420 [patent_doc_number] => 04849978 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-07-18 [patent_title] => 'Memory unit backup using checksum' [patent_app_type] => 1 [patent_app_number] => 7/068862 [patent_app_country] => US [patent_app_date] => 1987-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3758 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/849/04849978.pdf [firstpage_image] =>[orig_patent_app_number] => 068862 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/068862
Memory unit backup using checksum Jul 1, 1987 Issued
Array ( [id] => 2527512 [patent_doc_number] => 04870607 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-09-26 [patent_title] => 'Error detection carried out by the use of unused modulo-m code' [patent_app_type] => 1 [patent_app_number] => 7/069095 [patent_app_country] => US [patent_app_date] => 1987-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 11847 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/870/04870607.pdf [firstpage_image] =>[orig_patent_app_number] => 069095 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/069095
Error detection carried out by the use of unused modulo-m code Jul 1, 1987 Issued
07/069285 APPARATUS AND METHOD FOR DATA INDUCED CONDITION SIGNALING Jun 30, 1987 Abandoned
Array ( [id] => 2535638 [patent_doc_number] => 04888772 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-12-19 [patent_title] => 'Testing circuit for random access memory device' [patent_app_type] => 1 [patent_app_number] => 7/066275 [patent_app_country] => US [patent_app_date] => 1987-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 16800 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/888/04888772.pdf [firstpage_image] =>[orig_patent_app_number] => 066275 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/066275
Testing circuit for random access memory device Jun 24, 1987 Issued
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