Michael Robert Reid

Array ( [id] => 6788674 [patent_doc_number] => 20030139913 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-24 [patent_title] => 'Methods, systems, and computer program products for deriving a signal from a clock signal using alternate ratio frequency division' [patent_app_type] => new [patent_app_number] => 10/339280 [patent_app_country] => US [patent_app_date] => 2003-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3730 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0139/20030139913.pdf [firstpage_image] =>[orig_patent_app_number] => 10339280 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 663195 [patent_doc_number] => RE039252 [patent_country] => US [patent_kind] => E1 [patent_issue_date] => 2006-08-29 [patent_title] => 'Instruction dependent clock scheme' [patent_app_type] => reissue [patent_app_number] => 10/326169 [patent_app_country] => US [patent_app_date] => 2002-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3306 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/039/RE039252.pdf [firstpage_image] =>[orig_patent_app_number] => 10326169 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7465174 [patent_doc_number] => 20040120445 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-24 [patent_title] => 'Method and apparatus to limit current-change induced voltage changes in a microcircuit' [patent_app_type] => new [patent_app_number] => 10/327441 [patent_app_country] => US [patent_app_date] => 2002-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5276 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0120/20040120445.pdf [firstpage_image] =>[orig_patent_app_number] => 10327441 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7599999 [patent_doc_number] => 07386713 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-06-10 [patent_title] => 'On-chip security method and apparatus' [patent_app_type] => utility [patent_app_number] => 10/500131 [patent_app_country] => US [patent_app_date] => 2002-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3284 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/386/07386713.pdf [firstpage_image] =>[orig_patent_app_number] => 10500131 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 423682 [patent_doc_number] => 07275154 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-25 [patent_title] => 'Method of optimizing the performance of a computer and a main non-volatile memory unit optimized using specific-use sections' [patent_app_type] => utility [patent_app_number] => 10/496808 [patent_app_country] => US [patent_app_date] => 2002-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 14213 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 297 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/275/07275154.pdf [firstpage_image] =>[orig_patent_app_number] => 10496808 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6793375 [patent_doc_number] => 20030088719 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-08 [patent_title] => 'Method and apparatus for data transfer between at least two modules interconnected by a serial data bus' [patent_app_type] => new [patent_app_number] => 10/286046 [patent_app_country] => US [patent_app_date] => 2002-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2227 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0088/20030088719.pdf [firstpage_image] =>[orig_patent_app_number] => 10286046 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6712512 [patent_doc_number] => 20030172261 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-11 [patent_title] => 'System boot using NAND flash memory and method thereof' [patent_app_type] => new [patent_app_number] => 10/282400 [patent_app_country] => US [patent_app_date] => 2002-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6789 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20030172261.pdf [firstpage_image] =>[orig_patent_app_number] => 10282400 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 539647 [patent_doc_number] => 07188237 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-06 [patent_title] => 'Reboot manager usable to change firmware in a high availability single processor system' [patent_app_type] => utility [patent_app_number] => 10/282951 [patent_app_country] => US [patent_app_date] => 2002-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 8077 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/188/07188237.pdf [firstpage_image] =>[orig_patent_app_number] => 10282951 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7392036 [patent_doc_number] => 20040083398 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-29 [patent_title] => 'Methods and apparatus for setting a bus-to-core ratio of a multi-processor platform' [patent_app_type] => new [patent_app_number] => 10/282895 [patent_app_country] => US [patent_app_date] => 2002-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4780 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20040083398.pdf [firstpage_image] =>[orig_patent_app_number] => 10282895 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6871666 [patent_doc_number] => 20030084356 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-01 [patent_title] => 'Power control apparatus in a data communication network, and method therefor' [patent_app_type] => new [patent_app_number] => 10/282024 [patent_app_country] => US [patent_app_date] => 2002-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4791 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0084/20030084356.pdf [firstpage_image] =>[orig_patent_app_number] => 10282024 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 771516 [patent_doc_number] => 07010712 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-03-07 [patent_title] => 'Method and system for synchronizing serial data streams in multiple-port design' [patent_app_type] => utility [patent_app_number] => 10/282379 [patent_app_country] => US [patent_app_date] => 2002-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2692 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/010/07010712.pdf [firstpage_image] =>[orig_patent_app_number] => 10282379 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6871545 [patent_doc_number] => 20030084235 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-01 [patent_title] => 'Synchronous DRAM controller and control method for the same' [patent_app_type] => new [patent_app_number] => 10/278567 [patent_app_country] => US [patent_app_date] => 2002-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8388 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0084/20030084235.pdf [firstpage_image] =>[orig_patent_app_number] => 10278567 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 564048 [patent_doc_number] => 07167993 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-01-23 [patent_title] => 'Thermal and power management for computer systems' [patent_app_type] => utility [patent_app_number] => 10/277630 [patent_app_country] => US [patent_app_date] => 2002-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 5631 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/167/07167993.pdf [firstpage_image] =>[orig_patent_app_number] => 10277630 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7174692 [patent_doc_number] => 20040078615 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-22 [patent_title] => 'Multi-module system, distribution circuit and their methods of operation' [patent_app_type] => new [patent_app_number] => 10/274073 [patent_app_country] => US [patent_app_date] => 2002-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3927 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0078/20040078615.pdf [firstpage_image] =>[orig_patent_app_number] => 10274073 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6703170 [patent_doc_number] => 20030226050 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-04 [patent_title] => 'Power saving for mac ethernet control logic' [patent_app_type] => new [patent_app_number] => 10/168706 [patent_app_country] => US [patent_app_date] => 2002-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6766 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0226/20030226050.pdf [firstpage_image] =>[orig_patent_app_number] => 10168706 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 653664 [patent_doc_number] => 07114089 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-26 [patent_title] => 'System for controlling operation of a processor based on information contained within instruction word' [patent_app_type] => utility [patent_app_number] => 10/265508 [patent_app_country] => US [patent_app_date] => 2002-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5155 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/114/07114089.pdf [firstpage_image] =>[orig_patent_app_number] => 10265508 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6775500 [patent_doc_number] => 20030018838 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-23 [patent_title] => 'System for determining status of multiple interlocking FIFO buffer structures based on the position of at least one pointer of each of the multiple buffers' [patent_app_type] => new [patent_app_number] => 10/229727 [patent_app_country] => US [patent_app_date] => 2002-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2914 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0018/20030018838.pdf [firstpage_image] =>[orig_patent_app_number] => 10229727 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1206973 [patent_doc_number] => 06721894 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-04-13 [patent_title] => 'METHOD FOR CONTROLLING POWER OF A MICROPROCESSOR BY ASSERTING AND DE-ASSERTING A CONTROL SIGNAL IN RESPONSE CONDITIONS ASSOCIATED WITH THE MICROPROCESSOR ENTERING AND EXITING LOW POWER STATE RESPECTIVELY' [patent_app_type] => B2 [patent_app_number] => 10/216615 [patent_app_country] => US [patent_app_date] => 2002-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 4084 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/721/06721894.pdf [firstpage_image] =>[orig_patent_app_number] => 10216615 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7091984 [patent_doc_number] => 20050010830 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-13 [patent_title] => 'Power reduction in microprocessor systems' [patent_app_type] => utility [patent_app_number] => 10/486302 [patent_app_country] => US [patent_app_date] => 2002-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1990 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0010/20050010830.pdf [firstpage_image] =>[orig_patent_app_number] => 10486302 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6751934 [patent_doc_number] => 20030046455 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-06 [patent_title] => 'Multi-function module incorporating flash memory and enhanced I/O interface' [patent_app_type] => new [patent_app_number] => 10/211947 [patent_app_country] => US [patent_app_date] => 2002-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5394 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20030046455.pdf [firstpage_image] =>[orig_patent_app_number] => 10211947 [rel_patent_id] =>[rel_patent_doc_number] =>)