Michael Robert Reid

Array ( [id] => 554279 [patent_doc_number] => 07174475 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-06 [patent_title] => 'Method and apparatus for distributing a self-synchronized clock to nodes on a chip' [patent_app_type] => utility [patent_app_number] => 09/785604 [patent_app_country] => US [patent_app_date] => 2001-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 2956 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/174/07174475.pdf [firstpage_image] =>[orig_patent_app_number] => 09785604 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1011446 [patent_doc_number] => 06901520 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-31 [patent_title] => 'Power supply protection apparatus for computer system' [patent_app_type] => utility [patent_app_number] => 09/788253 [patent_app_country] => US [patent_app_date] => 2001-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7511 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/901/06901520.pdf [firstpage_image] =>[orig_patent_app_number] => 09788253 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5926740 [patent_doc_number] => 20020116652 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-22 [patent_title] => 'Integrated driver electronic (IDE) device power control' [patent_app_type] => new [patent_app_number] => 09/785927 [patent_app_country] => US [patent_app_date] => 2001-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3930 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0116/20020116652.pdf [firstpage_image] =>[orig_patent_app_number] => 09785927 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1236400 [patent_doc_number] => 06694443 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-17 [patent_title] => 'SYSTEM FOR CONTROLLING POWER OF A MICROPROCESSOR BY ASSERTING AND DE-ASSERTING A CONTROL SIGNAL IN RESPONSE TO CONDITION ASSOCIATED WITH THE MICROPROCESSOR ENTERING AND EXITING LOW POWER STATE RESPECTIVELY' [patent_app_type] => B1 [patent_app_number] => 09/779150 [patent_app_country] => US [patent_app_date] => 2001-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 5131 [patent_no_of_claims] => 84 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/694/06694443.pdf [firstpage_image] =>[orig_patent_app_number] => 09779150 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 995946 [patent_doc_number] => 06918050 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-07-12 [patent_title] => 'Delay adjustment circuit and a clock generating circuit using the same' [patent_app_type] => utility [patent_app_number] => 09/773595 [patent_app_country] => US [patent_app_date] => 2001-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 29 [patent_no_of_words] => 9366 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/918/06918050.pdf [firstpage_image] =>[orig_patent_app_number] => 09773595 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6020210 [patent_doc_number] => 20020104034 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-01 [patent_title] => 'Signal trace phase delay' [patent_app_type] => new [patent_app_number] => 09/771094 [patent_app_country] => US [patent_app_date] => 2001-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3583 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0104/20020104034.pdf [firstpage_image] =>[orig_patent_app_number] => 09771094 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1218289 [patent_doc_number] => 06711695 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-23 [patent_title] => 'PECL voltage DIMM with remote multi-module etch skew compensation' [patent_app_type] => B1 [patent_app_number] => 09/770590 [patent_app_country] => US [patent_app_date] => 2001-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4562 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/711/06711695.pdf [firstpage_image] =>[orig_patent_app_number] => 09770590 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6020225 [patent_doc_number] => 20020104035 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-01 [patent_title] => 'Method for reducing tuning etch in a clock-forwarded interface' [patent_app_type] => new [patent_app_number] => 09/770589 [patent_app_country] => US [patent_app_date] => 2001-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4291 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0104/20020104035.pdf [firstpage_image] =>[orig_patent_app_number] => 09770589 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6020094 [patent_doc_number] => 20020103993 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-01 [patent_title] => 'System and method for providing information to a computer system' [patent_app_type] => new [patent_app_number] => 09/770593 [patent_app_country] => US [patent_app_date] => 2001-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4695 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0103/20020103993.pdf [firstpage_image] =>[orig_patent_app_number] => 09770593 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 615794 [patent_doc_number] => 07149884 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-12-12 [patent_title] => 'Method and system for configuring a computer system via a wireless communication link' [patent_app_type] => utility [patent_app_number] => 09/770586 [patent_app_country] => US [patent_app_date] => 2001-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4067 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/149/07149884.pdf [firstpage_image] =>[orig_patent_app_number] => 09770586 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6553650 [patent_doc_number] => 20020138225 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-26 [patent_title] => 'Automatic configuration of delay parameters for memory controllers of slave processors' [patent_app_type] => new [patent_app_number] => 09/772113 [patent_app_country] => US [patent_app_date] => 2001-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6129 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20020138225.pdf [firstpage_image] =>[orig_patent_app_number] => 09772113 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5890360 [patent_doc_number] => 20020013895 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-31 [patent_title] => 'Price/performance base configuration sizer' [patent_app_type] => new [patent_app_number] => 09/766051 [patent_app_country] => US [patent_app_date] => 2001-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 10225 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20020013895.pdf [firstpage_image] =>[orig_patent_app_number] => 09766051 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1066818 [patent_doc_number] => 06851068 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-02-01 [patent_title] => 'System for remotely controlling power cycling of a peripheral expansion subsystem by a host' [patent_app_type] => utility [patent_app_number] => 09/764492 [patent_app_country] => US [patent_app_date] => 2001-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2948 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/851/06851068.pdf [firstpage_image] =>[orig_patent_app_number] => 09764492 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1075185 [patent_doc_number] => 06839853 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-01-04 [patent_title] => 'System for controlling power of computer depending on test result of a power-on self test' [patent_app_type] => utility [patent_app_number] => 09/760115 [patent_app_country] => US [patent_app_date] => 2001-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9053 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/839/06839853.pdf [firstpage_image] =>[orig_patent_app_number] => 09760115 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7605692 [patent_doc_number] => 07100030 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-08-29 [patent_title] => 'System for identifying, based on setup use history, and displaying a setup of a system to indicate enabled and disabled setting items to a user' [patent_app_type] => utility [patent_app_number] => 09/758376 [patent_app_country] => US [patent_app_date] => 2001-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 6268 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/100/07100030.pdf [firstpage_image] =>[orig_patent_app_number] => 09758376 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6888033 [patent_doc_number] => 20010009027 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-07-19 [patent_title] => 'Computer power supply startup apparatus' [patent_app_type] => new-utility [patent_app_number] => 09/760399 [patent_app_country] => US [patent_app_date] => 2001-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2574 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0009/20010009027.pdf [firstpage_image] =>[orig_patent_app_number] => 09760399 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6948316 [patent_doc_number] => 20010021953 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-09-13 [patent_title] => 'Data processing circuit' [patent_app_type] => new [patent_app_number] => 09/758425 [patent_app_country] => US [patent_app_date] => 2001-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 11349 [patent_no_of_claims] => 62 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0021/20010021953.pdf [firstpage_image] =>[orig_patent_app_number] => 09758425 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5791513 [patent_doc_number] => 20020161993 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-31 [patent_title] => 'Computer start up memory' [patent_app_type] => new [patent_app_number] => 09/751788 [patent_app_country] => US [patent_app_date] => 2000-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1761 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0161/20020161993.pdf [firstpage_image] =>[orig_patent_app_number] => 09751788 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 716985 [patent_doc_number] => 07058836 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-06 [patent_title] => 'Method and apparatus facilitating direct access to a parallel ATA device by an autonomous subsystem' [patent_app_type] => utility [patent_app_number] => 09/752062 [patent_app_country] => US [patent_app_date] => 2000-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3069 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/058/07058836.pdf [firstpage_image] =>[orig_patent_app_number] => 09752062 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7029695 [patent_doc_number] => 20010014922 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-16 [patent_title] => 'Interface circuit device for performing data sampling at optimum strobe timing' [patent_app_type] => new [patent_app_number] => 09/749509 [patent_app_country] => US [patent_app_date] => 2000-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 38 [patent_no_of_words] => 30133 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20010014922.pdf [firstpage_image] =>[orig_patent_app_number] => 09749509 [rel_patent_id] =>[rel_patent_doc_number] =>)