Search

Michael S. Chambers

Examiner (ID: 314, Phone: (571)272-4407 , Office: P/3711 )

Most Active Art Unit
3711
Art Unit(s)
3711
Total Applications
1277
Issued Applications
792
Pending Applications
53
Abandoned Applications
434

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1109804 [patent_doc_number] => 06813698 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-02 [patent_title] => 'Concurrent configuration of drives of a data storage library' [patent_app_type] => B2 [patent_app_number] => 09/970933 [patent_app_country] => US [patent_app_date] => 2001-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 6721 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/813/06813698.pdf [firstpage_image] =>[orig_patent_app_number] => 09970933 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/970933
Concurrent configuration of drives of a data storage library Oct 4, 2001 Issued
Array ( [id] => 238308 [patent_doc_number] => RE040921 [patent_country] => US [patent_kind] => E1 [patent_issue_date] => 2009-09-22 [patent_title] => 'Mechanism for efficiently processing deferred order-dependent memory access transactions in a pipelined system' [patent_app_type] => reissue [patent_app_number] => 09/972704 [patent_app_country] => US [patent_app_date] => 2001-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3465 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/040/RE040921.pdf [firstpage_image] =>[orig_patent_app_number] => 09972704 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/972704
Mechanism for efficiently processing deferred order-dependent memory access transactions in a pipelined system Oct 3, 2001 Issued
Array ( [id] => 1297089 [patent_doc_number] => 06633955 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-14 [patent_title] => 'Four way support for dynamic mirror service policy' [patent_app_type] => B1 [patent_app_number] => 09/965421 [patent_app_country] => US [patent_app_date] => 2001-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 7808 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/633/06633955.pdf [firstpage_image] =>[orig_patent_app_number] => 09965421 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/965421
Four way support for dynamic mirror service policy Sep 26, 2001 Issued
Array ( [id] => 6675850 [patent_doc_number] => 20030061453 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-27 [patent_title] => 'Method and apparatus for arbitrating a memory bus' [patent_app_type] => new [patent_app_number] => 09/965387 [patent_app_country] => US [patent_app_date] => 2001-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4196 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20030061453.pdf [firstpage_image] =>[orig_patent_app_number] => 09965387 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/965387
Method and apparatus for arbitrating a memory bus Sep 26, 2001 Abandoned
Array ( [id] => 1169925 [patent_doc_number] => 06766420 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-07-20 [patent_title] => 'Selectively powering portions of system memory in a network server to conserve energy' [patent_app_type] => B2 [patent_app_number] => 09/965008 [patent_app_country] => US [patent_app_date] => 2001-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3348 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/766/06766420.pdf [firstpage_image] =>[orig_patent_app_number] => 09965008 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/965008
Selectively powering portions of system memory in a network server to conserve energy Sep 26, 2001 Issued
Array ( [id] => 6675856 [patent_doc_number] => 20030061459 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-27 [patent_title] => 'Method and apparatus for memory access scheduling to reduce memory access latency' [patent_app_type] => new [patent_app_number] => 09/966957 [patent_app_country] => US [patent_app_date] => 2001-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 7767 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 18 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20030061459.pdf [firstpage_image] =>[orig_patent_app_number] => 09966957 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/966957
Method and apparatus for memory access scheduling to reduce memory access latency Sep 26, 2001 Issued
Array ( [id] => 6675848 [patent_doc_number] => 20030061451 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-27 [patent_title] => 'Method and system for web caching based on predictive usage' [patent_app_type] => new [patent_app_number] => 09/965502 [patent_app_country] => US [patent_app_date] => 2001-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3594 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20030061451.pdf [firstpage_image] =>[orig_patent_app_number] => 09965502 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/965502
Method and system for web caching based on predictive usage Sep 26, 2001 Issued
Array ( [id] => 7622374 [patent_doc_number] => 06687792 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-02-03 [patent_title] => 'Method and system for selectively caching web elements' [patent_app_type] => B2 [patent_app_number] => 09/965362 [patent_app_country] => US [patent_app_date] => 2001-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2734 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 6 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/687/06687792.pdf [firstpage_image] =>[orig_patent_app_number] => 09965362 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/965362
Method and system for selectively caching web elements Sep 26, 2001 Issued
Array ( [id] => 6675847 [patent_doc_number] => 20030061450 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-27 [patent_title] => 'List based method and apparatus for selective and rapid cache flushes' [patent_app_type] => new [patent_app_number] => 09/967031 [patent_app_country] => US [patent_app_date] => 2001-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4111 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20030061450.pdf [firstpage_image] =>[orig_patent_app_number] => 09967031 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/967031
List based method and apparatus for selective and rapid cache flushes Sep 26, 2001 Issued
Array ( [id] => 6294265 [patent_doc_number] => 20020056020 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-09 [patent_title] => 'Enhanced dram with embedded registers' [patent_app_type] => new [patent_app_number] => 09/962287 [patent_app_country] => US [patent_app_date] => 2001-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 14841 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0056/20020056020.pdf [firstpage_image] =>[orig_patent_app_number] => 09962287 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/962287
Enhanced DRAM with embedded registers Sep 23, 2001 Issued
Array ( [id] => 6413916 [patent_doc_number] => 20020038408 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-28 [patent_title] => 'Data consistency memory management system and method and associated multiprocessor network' [patent_app_type] => new [patent_app_number] => 09/956422 [patent_app_country] => US [patent_app_date] => 2001-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5131 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20020038408.pdf [firstpage_image] =>[orig_patent_app_number] => 09956422 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/956422
Data consistency memory management system and method and associated multiprocessor network Sep 18, 2001 Issued
Array ( [id] => 5971446 [patent_doc_number] => 20020091903 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-11 [patent_title] => 'Disk control system and method' [patent_app_type] => new [patent_app_number] => 09/954303 [patent_app_country] => US [patent_app_date] => 2001-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 12711 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0091/20020091903.pdf [firstpage_image] =>[orig_patent_app_number] => 09954303 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/954303
Disk control system and method Sep 17, 2001 Issued
Array ( [id] => 998919 [patent_doc_number] => 06915335 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-07-05 [patent_title] => 'Serial protocol for efficient messaging between host and intelligent daughtercards over a serial link' [patent_app_type] => utility [patent_app_number] => 09/955004 [patent_app_country] => US [patent_app_date] => 2001-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 2907 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/915/06915335.pdf [firstpage_image] =>[orig_patent_app_number] => 09955004 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/955004
Serial protocol for efficient messaging between host and intelligent daughtercards over a serial link Sep 16, 2001 Issued
Array ( [id] => 5890225 [patent_doc_number] => 20020013822 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-31 [patent_title] => 'Shared as needed programming model' [patent_app_type] => new [patent_app_number] => 09/915002 [patent_app_country] => US [patent_app_date] => 2001-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3992 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20020013822.pdf [firstpage_image] =>[orig_patent_app_number] => 09915002 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/915002
Shared as needed programming model Jul 24, 2001 Abandoned
Array ( [id] => 6836060 [patent_doc_number] => 20030163606 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-28 [patent_title] => 'High-speed memory system' [patent_app_type] => new [patent_app_number] => 10/311687 [patent_app_country] => US [patent_app_date] => 2003-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 6888 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 18 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0163/20030163606.pdf [firstpage_image] =>[orig_patent_app_number] => 10311687 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/311687
High-speed memory system Jun 19, 2001 Issued
Array ( [id] => 1052475 [patent_doc_number] => 06862606 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-03-01 [patent_title] => 'System and method for partitioning address space in a proxy cache server cluster' [patent_app_type] => utility [patent_app_number] => 09/877918 [patent_app_country] => US [patent_app_date] => 2001-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6437 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/862/06862606.pdf [firstpage_image] =>[orig_patent_app_number] => 09877918 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/877918
System and method for partitioning address space in a proxy cache server cluster Jun 6, 2001 Issued
Array ( [id] => 1430370 [patent_doc_number] => 06526486 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-02-25 [patent_title] => 'Method of managing messages in a computer memory' [patent_app_type] => B2 [patent_app_number] => 09/871866 [patent_app_country] => US [patent_app_date] => 2001-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3425 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/526/06526486.pdf [firstpage_image] =>[orig_patent_app_number] => 09871866 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/871866
Method of managing messages in a computer memory May 31, 2001 Issued
Array ( [id] => 6422151 [patent_doc_number] => 20020184216 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-05 [patent_title] => 'Method and apparatus for reducing latency and message traffic during data and lock transfer in a multi-node system' [patent_app_type] => new [patent_app_number] => 09/871853 [patent_app_country] => US [patent_app_date] => 2001-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 10004 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0184/20020184216.pdf [firstpage_image] =>[orig_patent_app_number] => 09871853 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/871853
Method and apparatus for reducing latency and message traffic during data and lock transfer in a multi-node system May 30, 2001 Issued
Array ( [id] => 6988694 [patent_doc_number] => 20010037437 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-01 [patent_title] => 'Information processing device' [patent_app_type] => new [patent_app_number] => 09/860143 [patent_app_country] => US [patent_app_date] => 2001-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6023 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20010037437.pdf [firstpage_image] =>[orig_patent_app_number] => 09860143 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/860143
Information processing device May 16, 2001 Abandoned
Array ( [id] => 1326847 [patent_doc_number] => 06609185 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-08-19 [patent_title] => 'Data storage system having majority gate filter' [patent_app_type] => B1 [patent_app_number] => 09/859605 [patent_app_country] => US [patent_app_date] => 2001-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 47 [patent_no_of_words] => 26572 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/609/06609185.pdf [firstpage_image] =>[orig_patent_app_number] => 09859605 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/859605
Data storage system having majority gate filter May 16, 2001 Issued
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