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Michael S. Leslie

Examiner (ID: 13541)

Most Active Art Unit
3745
Art Unit(s)
3745
Total Applications
2490
Issued Applications
2101
Pending Applications
85
Abandoned Applications
332

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11307749 [patent_doc_number] => 09515155 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-12-06 [patent_title] => 'E-fuse design for high-K metal-gate technology' [patent_app_type] => utility [patent_app_number] => 14/136815 [patent_app_country] => US [patent_app_date] => 2013-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7668 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14136815 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/136815
E-fuse design for high-K metal-gate technology Dec 19, 2013 Issued
Array ( [id] => 11391809 [patent_doc_number] => 09553059 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-24 [patent_title] => 'Backside redistribution layer (RDL) structure' [patent_app_type] => utility [patent_app_number] => 14/137231 [patent_app_country] => US [patent_app_date] => 2013-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 26 [patent_no_of_words] => 3955 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14137231 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/137231
Backside redistribution layer (RDL) structure Dec 19, 2013 Issued
Array ( [id] => 10294740 [patent_doc_number] => 20150179740 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-25 [patent_title] => 'TRANSISTOR DEVICE WITH STRAINED LAYER' [patent_app_type] => utility [patent_app_number] => 14/136420 [patent_app_country] => US [patent_app_date] => 2013-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4624 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14136420 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/136420
TRANSISTOR DEVICE WITH STRAINED LAYER Dec 19, 2013 Abandoned
Array ( [id] => 11333710 [patent_doc_number] => 09524962 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-12-20 [patent_title] => 'Semiconductor device comprising an e-fuse and a FET' [patent_app_type] => utility [patent_app_number] => 14/136581 [patent_app_country] => US [patent_app_date] => 2013-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 5849 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14136581 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/136581
Semiconductor device comprising an e-fuse and a FET Dec 19, 2013 Issued
Array ( [id] => 10294935 [patent_doc_number] => 20150179934 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-25 [patent_title] => 'ZrOx/STO/ZrOx Based Selector Element' [patent_app_type] => utility [patent_app_number] => 14/136465 [patent_app_country] => US [patent_app_date] => 2013-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10992 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14136465 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/136465
ZrOx/STO/ZrOx Based Selector Element Dec 19, 2013 Abandoned
Array ( [id] => 11740204 [patent_doc_number] => 09704798 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-11 [patent_title] => 'Using materials with different etch rates to fill trenches in semiconductor devices' [patent_app_type] => utility [patent_app_number] => 14/137497 [patent_app_country] => US [patent_app_date] => 2013-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 6101 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14137497 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/137497
Using materials with different etch rates to fill trenches in semiconductor devices Dec 19, 2013 Issued
Array ( [id] => 10294563 [patent_doc_number] => 20150179562 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-25 [patent_title] => 'THICKENED STRESS RELIEF AND POWER DISTRIBUTION LAYER' [patent_app_type] => utility [patent_app_number] => 14/137487 [patent_app_country] => US [patent_app_date] => 2013-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5021 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14137487 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/137487
Thickened stress relief and power distribution layer Dec 19, 2013 Issued
Array ( [id] => 11214864 [patent_doc_number] => 09443906 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-13 [patent_title] => 'TiOx based selector element' [patent_app_type] => utility [patent_app_number] => 14/136365 [patent_app_country] => US [patent_app_date] => 2013-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 11877 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14136365 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/136365
TiOx based selector element Dec 19, 2013 Issued
Array ( [id] => 11539711 [patent_doc_number] => 09614131 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-04 [patent_title] => 'Optoelectronic semiconductor component and method for producing an optoelectronic semiconductor component' [patent_app_type] => utility [patent_app_number] => 14/650545 [patent_app_country] => US [patent_app_date] => 2013-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 6216 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14650545 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/650545
Optoelectronic semiconductor component and method for producing an optoelectronic semiconductor component Dec 10, 2013 Issued
Array ( [id] => 13146071 [patent_doc_number] => 10090376 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-02 [patent_title] => Methods of forming semiconductor device structures, and methods of forming capacitor structures [patent_app_type] => utility [patent_app_number] => 14/065662 [patent_app_country] => US [patent_app_date] => 2013-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8346 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14065662 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/065662
Methods of forming semiconductor device structures, and methods of forming capacitor structures Oct 28, 2013 Issued
Array ( [id] => 10208872 [patent_doc_number] => 20150093862 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-02 [patent_title] => 'INTERFACE TREATMENT OF SEMICONDUCTOR SURFACES WITH HIGH DENSITY LOW ENERGY PLASMA' [patent_app_type] => utility [patent_app_number] => 14/064933 [patent_app_country] => US [patent_app_date] => 2013-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5594 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14064933 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/064933
Interface treatment of semiconductor surfaces with high density low energy plasma Oct 27, 2013 Issued
Array ( [id] => 10178860 [patent_doc_number] => 09209072 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-08 [patent_title] => 'Global dielectric and barrier layer' [patent_app_type] => utility [patent_app_number] => 14/063175 [patent_app_country] => US [patent_app_date] => 2013-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4054 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14063175 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/063175
Global dielectric and barrier layer Oct 24, 2013 Issued
Array ( [id] => 10226380 [patent_doc_number] => 20150111373 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-23 [patent_title] => 'REDUCING GATE HEIGHT VARIATION IN RMG PROCESS' [patent_app_type] => utility [patent_app_number] => 14/057357 [patent_app_country] => US [patent_app_date] => 2013-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4176 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14057357 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/057357
REDUCING GATE HEIGHT VARIATION IN RMG PROCESS Oct 17, 2013 Abandoned
Array ( [id] => 10226381 [patent_doc_number] => 20150111374 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-23 [patent_title] => 'SURFACE TREATMENT IN A DEP-ETCH-DEP PROCESS' [patent_app_type] => utility [patent_app_number] => 14/057529 [patent_app_country] => US [patent_app_date] => 2013-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4198 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14057529 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/057529
SURFACE TREATMENT IN A DEP-ETCH-DEP PROCESS Oct 17, 2013 Abandoned
Array ( [id] => 11207866 [patent_doc_number] => 09437497 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-06 [patent_title] => 'Method of making a FinFET device' [patent_app_type] => utility [patent_app_number] => 14/057789 [patent_app_country] => US [patent_app_date] => 2013-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 3882 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 292 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14057789 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/057789
Method of making a FinFET device Oct 17, 2013 Issued
Array ( [id] => 10226317 [patent_doc_number] => 20150111311 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-23 [patent_title] => 'METHOD OF SELECTIVELY REMOVING SILICON NITRIDE AND ETCHING APPARATUS THEREOF' [patent_app_type] => utility [patent_app_number] => 14/056673 [patent_app_country] => US [patent_app_date] => 2013-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2903 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14056673 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/056673
Method of selectively removing silicon nitride and etching apparatus thereof Oct 16, 2013 Issued
Array ( [id] => 11818119 [patent_doc_number] => 09722083 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-01 [patent_title] => 'Source/drain junction formation' [patent_app_type] => utility [patent_app_number] => 14/056711 [patent_app_country] => US [patent_app_date] => 2013-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 5273 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14056711 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/056711
Source/drain junction formation Oct 16, 2013 Issued
Array ( [id] => 10537913 [patent_doc_number] => 09263551 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-16 [patent_title] => 'Simultaneous formation of source/drain openings with different profiles' [patent_app_type] => utility [patent_app_number] => 14/052160 [patent_app_country] => US [patent_app_date] => 2013-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4381 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14052160 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/052160
Simultaneous formation of source/drain openings with different profiles Oct 10, 2013 Issued
Array ( [id] => 11765068 [patent_doc_number] => 09373514 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-06-21 [patent_title] => 'Non-volatile FINFET memory array and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 14/051584 [patent_app_country] => US [patent_app_date] => 2013-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 4785 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14051584 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/051584
Non-volatile FINFET memory array and manufacturing method thereof Oct 10, 2013 Issued
Array ( [id] => 10537597 [patent_doc_number] => 09263231 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-16 [patent_title] => 'Moveable current sensor for increasing ion beam utilization during ion implantation' [patent_app_type] => utility [patent_app_number] => 14/050952 [patent_app_country] => US [patent_app_date] => 2013-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 5661 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14050952 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/050952
Moveable current sensor for increasing ion beam utilization during ion implantation Oct 9, 2013 Issued
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