Search

Michael Sun

Examiner (ID: 15971, Phone: (571)270-1724 , Office: P/2184 )

Most Active Art Unit
2184
Art Unit(s)
2183, 2184
Total Applications
1048
Issued Applications
915
Pending Applications
46
Abandoned Applications
111

Applications

Application numberTitle of the applicationFiling DateStatus
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17/207885
Mobile de-whitening Mar 21, 2021 Issued
Array ( [id] => 16950233 [patent_doc_number] => 20210208925 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-08 [patent_title] => METHOD AND APPARATUS FOR EXECUTING NON-MASKABLE INTERRUPT [patent_app_type] => utility [patent_app_number] => 17/207186 [patent_app_country] => US [patent_app_date] => 2021-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8582 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17207186 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/207186
Method and apparatus for executing non-maskable interrupt Mar 18, 2021 Issued
Array ( [id] => 18087401 [patent_doc_number] => 11537537 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-27 [patent_title] => Semiconductor device and method [patent_app_type] => utility [patent_app_number] => 17/200427 [patent_app_country] => US [patent_app_date] => 2021-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 24 [patent_no_of_words] => 22718 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17200427 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/200427
Semiconductor device and method Mar 11, 2021 Issued
Array ( [id] => 17100859 [patent_doc_number] => 20210288650 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-16 [patent_title] => SEMICONDUCTOR DEVICE AND CIRCUIT LAYOUT METHOD [patent_app_type] => utility [patent_app_number] => 17/199587 [patent_app_country] => US [patent_app_date] => 2021-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15403 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17199587 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/199587
SEMICONDUCTOR DEVICE AND CIRCUIT LAYOUT METHOD Mar 11, 2021 Abandoned
Array ( [id] => 18046763 [patent_doc_number] => 11520717 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-12-06 [patent_title] => Memory tiles in data processing engine array [patent_app_type] => utility [patent_app_number] => 17/196669 [patent_app_country] => US [patent_app_date] => 2021-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 27 [patent_no_of_words] => 30732 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17196669 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/196669
Memory tiles in data processing engine array Mar 8, 2021 Issued
Array ( [id] => 17846795 [patent_doc_number] => 11436168 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-06 [patent_title] => Accelerator and electronic device including the same [patent_app_type] => utility [patent_app_number] => 17/192032 [patent_app_country] => US [patent_app_date] => 2021-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8323 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17192032 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/192032
Accelerator and electronic device including the same Mar 3, 2021 Issued
Array ( [id] => 17817209 [patent_doc_number] => 11422820 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-23 [patent_title] => Shadow cache for securing conditional speculative instruction execution [patent_app_type] => utility [patent_app_number] => 17/189151 [patent_app_country] => US [patent_app_date] => 2021-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5110 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17189151 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/189151
Shadow cache for securing conditional speculative instruction execution Feb 28, 2021 Issued
Array ( [id] => 17550245 [patent_doc_number] => 20220121587 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-21 [patent_title] => Identification and Classification of Write Stream Priority [patent_app_type] => utility [patent_app_number] => 17/187046 [patent_app_country] => US [patent_app_date] => 2021-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8286 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17187046 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/187046
Identification and classification of write stream priority Feb 25, 2021 Issued
Array ( [id] => 16918630 [patent_doc_number] => 20210191722 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-24 [patent_title] => USING LOOP EXIT PREDICTION TO ACCELERATE OR SUPPRESS LOOP MODE OF A PROCESSOR [patent_app_type] => utility [patent_app_number] => 17/169053 [patent_app_country] => US [patent_app_date] => 2021-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5783 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17169053 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/169053
Using loop exit prediction to accelerate or suppress loop mode of a processor Feb 4, 2021 Issued
Array ( [id] => 17557804 [patent_doc_number] => 11314508 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-04-26 [patent_title] => FPGA-based computing system for processing data in size, weight, and power constrained environments [patent_app_type] => utility [patent_app_number] => 17/163754 [patent_app_country] => US [patent_app_date] => 2021-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6611 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17163754 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/163754
FPGA-based computing system for processing data in size, weight, and power constrained environments Jan 31, 2021 Issued
Array ( [id] => 16856854 [patent_doc_number] => 20210157599 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-27 [patent_title] => CACHE SYSTEMS AND CIRCUITS FOR SYNCING CACHES OR CACHE SETS [patent_app_type] => utility [patent_app_number] => 17/163163 [patent_app_country] => US [patent_app_date] => 2021-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 46372 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17163163 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/163163
Cache systems and circuits for syncing caches or cache sets Jan 28, 2021 Issued
Array ( [id] => 16848930 [patent_doc_number] => 20210149675 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-20 [patent_title] => Extended Tags for Speculative and Normal Executions [patent_app_type] => utility [patent_app_number] => 17/158999 [patent_app_country] => US [patent_app_date] => 2021-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 46364 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17158999 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/158999
Extended tags for speculative and normal executions Jan 25, 2021 Issued
Array ( [id] => 16810571 [patent_doc_number] => 20210133126 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-06 [patent_title] => INFORMATION INTEGRATION APPARATUS [patent_app_type] => utility [patent_app_number] => 17/149024 [patent_app_country] => US [patent_app_date] => 2021-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3686 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17149024 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/149024
Information integration apparatus Jan 13, 2021 Issued
Array ( [id] => 17706958 [patent_doc_number] => 20220206964 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => EMULATING A LOCAL STORAGE BY ACCESSING AN EXTERNAL STORAGE THROUGH A SHARED PORT OF A NIC [patent_app_type] => utility [patent_app_number] => 17/145319 [patent_app_country] => US [patent_app_date] => 2021-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15889 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17145319 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/145319
Emulating a local storage by accessing an external storage through a shared port of a NIC Jan 8, 2021 Issued
Array ( [id] => 16794766 [patent_doc_number] => 20210124583 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-29 [patent_title] => Conditional Branch Frame Barrier [patent_app_type] => utility [patent_app_number] => 17/143145 [patent_app_country] => US [patent_app_date] => 2021-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18263 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 312 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17143145 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/143145
Conditional branch frame barrier Jan 5, 2021 Issued
Array ( [id] => 18276099 [patent_doc_number] => 11615043 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-28 [patent_title] => Systems, methods, and apparatus to enable data aggregation and adaptation in hardware acceleration subsystems [patent_app_type] => utility [patent_app_number] => 17/139970 [patent_app_country] => US [patent_app_date] => 2020-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 12989 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17139970 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/139970
Systems, methods, and apparatus to enable data aggregation and adaptation in hardware acceleration subsystems Dec 30, 2020 Issued
Array ( [id] => 17542885 [patent_doc_number] => 11308008 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-04-19 [patent_title] => Systems and methods for handling DPI messages outgoing from an emulator system [patent_app_type] => utility [patent_app_number] => 17/139333 [patent_app_country] => US [patent_app_date] => 2020-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9170 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17139333 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/139333
Systems and methods for handling DPI messages outgoing from an emulator system Dec 30, 2020 Issued
Array ( [id] => 18480055 [patent_doc_number] => 11693795 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-04 [patent_title] => Methods and apparatus to extend local buffer of a hardware accelerator [patent_app_type] => utility [patent_app_number] => 17/138740 [patent_app_country] => US [patent_app_date] => 2020-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 14204 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17138740 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/138740
Methods and apparatus to extend local buffer of a hardware accelerator Dec 29, 2020 Issued
Array ( [id] => 16764177 [patent_doc_number] => 20210109758 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-15 [patent_title] => POST COMPLETION EXECUTION IN AN OUT-OF-ORDER PROCESSOR DESIGN [patent_app_type] => utility [patent_app_number] => 17/128501 [patent_app_country] => US [patent_app_date] => 2020-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5802 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17128501 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/128501
Post completion execution in an out-of-order processor design Dec 20, 2020 Issued
Array ( [id] => 18864241 [patent_doc_number] => 20230418677 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-28 [patent_title] => PREEMPTION IN A MACHINE LEARNING HARDWARE ACCELERATOR [patent_app_type] => utility [patent_app_number] => 18/036506 [patent_app_country] => US [patent_app_date] => 2020-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9180 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18036506 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/036506
Preemption in a machine learning hardware accelerator Dec 20, 2020 Issued
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