
Michael Sun
Examiner (ID: 1348, Phone: (571)270-1724 , Office: P/2184 )
| Most Active Art Unit | 2184 |
| Art Unit(s) | 2184, 2183 |
| Total Applications | 1016 |
| Issued Applications | 892 |
| Pending Applications | 48 |
| Abandoned Applications | 110 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 15998165
[patent_doc_number] => 20200174953
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-06-04
[patent_title] => METHODS AND APPARATUS FOR SYNCHRONIZING UPLINK AND DOWNLINK TRANSACTIONS ON AN INTER-DEVICE COMMUNICATION LINK
[patent_app_type] => utility
[patent_app_number] => 16/780743
[patent_app_country] => US
[patent_app_date] => 2020-02-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8534
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16780743
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/780743 | Methods and apparatus for synchronizing uplink and downlink transactions on an inter-device communication link | Feb 2, 2020 | Issued |
Array
(
[id] => 17009311
[patent_doc_number] => 20210240472
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-08-05
[patent_title] => OVERLAPPED-IMMEDIATE/REGISTER-FIELD-SPECIFYING INSTRUCTION
[patent_app_type] => utility
[patent_app_number] => 16/776730
[patent_app_country] => US
[patent_app_date] => 2020-01-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7518
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 196
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16776730
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/776730 | Overlapped-immediate/register-field-specifying instruction | Jan 29, 2020 | Issued |
Array
(
[id] => 15939227
[patent_doc_number] => 20200161247
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-05-21
[patent_title] => INTEGRATION OF A PROGRAMMABLE DEVICE AND A PROCESSING SYSTEM IN AN INTEGRATED CIRCUIT PACKAGE
[patent_app_type] => utility
[patent_app_number] => 16/773501
[patent_app_country] => US
[patent_app_date] => 2020-01-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10412
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16773501
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/773501 | Integration of a programmable device and a processing system in an integrated circuit package | Jan 26, 2020 | Issued |
Array
(
[id] => 16116661
[patent_doc_number] => 20200210353
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-07-02
[patent_title] => COMPUTING TILE
[patent_app_type] => utility
[patent_app_number] => 16/746048
[patent_app_country] => US
[patent_app_date] => 2020-01-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10984
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 69
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16746048
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/746048 | Computing tile | Jan 16, 2020 | Issued |
Array
(
[id] => 17001252
[patent_doc_number] => 11080062
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-08-03
[patent_title] => Address manipulation using indices and tags
[patent_app_type] => utility
[patent_app_number] => 16/739540
[patent_app_country] => US
[patent_app_date] => 2020-01-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 12437
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 152
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16739540
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/739540 | Address manipulation using indices and tags | Jan 9, 2020 | Issued |
Array
(
[id] => 16921694
[patent_doc_number] => 20210194786
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-06-24
[patent_title] => PORT-TO-PORT NETWORK ROUTING USING A STORAGE DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/724602
[patent_app_country] => US
[patent_app_date] => 2019-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5471
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16724602
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/724602 | Port-to-port network routing using a storage device | Dec 22, 2019 | Issued |
Array
(
[id] => 17415782
[patent_doc_number] => 20220050686
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-02-17
[patent_title] => INSTRUCTION DRIVEN DYNAMIC CLOCK MANAGEMENT FOR DEEP PIPELINE AND OUT-OF-ORDER OPERATION OF MICROPROCESSOR USING ON-CHIP CRITICAL PATH MESSENGER AND ELASTIC PIPELINE CLOCKING
[patent_app_type] => utility
[patent_app_number] => 17/415494
[patent_app_country] => US
[patent_app_date] => 2019-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3406
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 192
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17415494
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/415494 | Instruction driven dynamic clock management for deep pipeline and out-of-order operation of microprocessor using on-chip critical path messenger and elastic pipeline clocking | Dec 17, 2019 | Issued |
Array
(
[id] => 15870689
[patent_doc_number] => 20200142748
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-05-07
[patent_title] => COMPUTATION METHOD AND PRODUCT THEREOF
[patent_app_type] => utility
[patent_app_number] => 16/718742
[patent_app_country] => US
[patent_app_date] => 2019-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 36223
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 212
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16718742
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/718742 | Computation method and product thereof | Dec 17, 2019 | Issued |
Array
(
[id] => 15773193
[patent_doc_number] => 20200117614
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-04-16
[patent_title] => COMPUTING DEVICE AND METHOD
[patent_app_type] => utility
[patent_app_number] => 16/715235
[patent_app_country] => US
[patent_app_date] => 2019-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 27688
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 255
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16715235
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/715235 | Computing device and method | Dec 15, 2019 | Issued |
Array
(
[id] => 16446858
[patent_doc_number] => 10838787
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-11-17
[patent_title] => Processing system with interspersed processors with multi-layer interconnect
[patent_app_type] => utility
[patent_app_number] => 16/713812
[patent_app_country] => US
[patent_app_date] => 2019-12-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 26
[patent_no_of_words] => 19879
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16713812
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/713812 | Processing system with interspersed processors with multi-layer interconnect | Dec 12, 2019 | Issued |
Array
(
[id] => 18046751
[patent_doc_number] => 11520705
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2022-12-06
[patent_title] => Input/output (I/O) memory management unit (IOMMU) multi-core interference mitigation
[patent_app_type] => utility
[patent_app_number] => 16/697536
[patent_app_country] => US
[patent_app_date] => 2019-11-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 2654
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 189
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16697536
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/697536 | Input/output (I/O) memory management unit (IOMMU) multi-core interference mitigation | Nov 26, 2019 | Issued |
Array
(
[id] => 19398851
[patent_doc_number] => 12073222
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-08-27
[patent_title] => Instruction ordering
[patent_app_type] => utility
[patent_app_number] => 17/593018
[patent_app_country] => US
[patent_app_date] => 2019-11-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 20
[patent_no_of_words] => 10179
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17593018
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/593018 | Instruction ordering | Nov 25, 2019 | Issued |
Array
(
[id] => 18276351
[patent_doc_number] => 11615295
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-03-28
[patent_title] => Distributed AI training topology based on flexible cable connection
[patent_app_type] => utility
[patent_app_number] => 16/622789
[patent_app_country] => US
[patent_app_date] => 2019-11-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 13
[patent_no_of_words] => 5763
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16622789
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/622789 | Distributed AI training topology based on flexible cable connection | Nov 14, 2019 | Issued |
Array
(
[id] => 16972346
[patent_doc_number] => 11068318
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-07-20
[patent_title] => Dynamic thread status retrieval using inter-thread communication
[patent_app_type] => utility
[patent_app_number] => 16/673999
[patent_app_country] => US
[patent_app_date] => 2019-11-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 10225
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 173
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16673999
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/673999 | Dynamic thread status retrieval using inter-thread communication | Nov 4, 2019 | Issued |
Array
(
[id] => 15594271
[patent_doc_number] => 20200073670
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-03-05
[patent_title] => INFINITE PROCESSOR THREAD BALANCING
[patent_app_type] => utility
[patent_app_number] => 16/674237
[patent_app_country] => US
[patent_app_date] => 2019-11-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6680
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16674237
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/674237 | Infinite processor thread balancing | Nov 4, 2019 | Issued |
Array
(
[id] => 15530877
[patent_doc_number] => 20200057744
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-02-20
[patent_title] => WIDE PROGRAMMABLE GAIN RECEIVER DATA PATH FOR SINGLE-ENDED MEMORY INTERFACE APPLICATION
[patent_app_type] => utility
[patent_app_number] => 16/661081
[patent_app_country] => US
[patent_app_date] => 2019-10-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12267
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16661081
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/661081 | Wide programmable gain receiver data path for single-ended memory interface application | Oct 22, 2019 | Issued |
Array
(
[id] => 15837799
[patent_doc_number] => 20200134182
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-04-30
[patent_title] => METHOD AND APPARATUS FOR UPDATING SHARED DATA IN A MULTI-CORE PROCESSOR ENVIRONMENT
[patent_app_type] => utility
[patent_app_number] => 16/660563
[patent_app_country] => US
[patent_app_date] => 2019-10-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8022
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16660563
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/660563 | Method and apparatus for updating shared data in a multi-core processor environment | Oct 21, 2019 | Issued |
Array
(
[id] => 16780124
[patent_doc_number] => 20210117203
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-04-22
[patent_title] => SPECULATIVE EXECUTION USING A PAGE-LEVEL TRACKED LOAD ORDER QUEUE
[patent_app_type] => utility
[patent_app_number] => 16/658688
[patent_app_country] => US
[patent_app_date] => 2019-10-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5813
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 71
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16658688
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/658688 | Speculative execution using a page-level tracked load order queue | Oct 20, 2019 | Issued |
Array
(
[id] => 16780125
[patent_doc_number] => 20210117204
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-04-22
[patent_title] => ONLINE INSTRUCTION TAGGING
[patent_app_type] => utility
[patent_app_number] => 16/658490
[patent_app_country] => US
[patent_app_date] => 2019-10-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 19986
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 251
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16658490
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/658490 | Online instruction tagging | Oct 20, 2019 | Issued |
Array
(
[id] => 16787960
[patent_doc_number] => 10990393
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2021-04-27
[patent_title] => Address-based filtering for load/store speculation
[patent_app_type] => utility
[patent_app_number] => 16/658474
[patent_app_country] => US
[patent_app_date] => 2019-10-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 8513
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16658474
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/658474 | Address-based filtering for load/store speculation | Oct 20, 2019 | Issued |