Search

Michael Sun

Examiner (ID: 1348, Phone: (571)270-1724 , Office: P/2184 )

Most Active Art Unit
2184
Art Unit(s)
2184, 2183
Total Applications
1016
Issued Applications
892
Pending Applications
48
Abandoned Applications
110

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16160913 [patent_doc_number] => 20200218689 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-09 [patent_title] => PIPELINING MULTI-DIRECTIONAL REDUCTION [patent_app_type] => utility [patent_app_number] => 16/241765 [patent_app_country] => US [patent_app_date] => 2019-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7049 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16241765 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/241765
Pipelining multi-directional reduction Jan 6, 2019 Issued
Array ( [id] => 15059103 [patent_doc_number] => 10459857 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-29 [patent_title] => Data receiving apparatus, data transmission and reception system, and control method of data transmission and reception system [patent_app_type] => utility [patent_app_number] => 16/240840 [patent_app_country] => US [patent_app_date] => 2019-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 5819 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16240840 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/240840
Data receiving apparatus, data transmission and reception system, and control method of data transmission and reception system Jan 6, 2019 Issued
Array ( [id] => 14282273 [patent_doc_number] => 20190138421 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-09 [patent_title] => REAL-TIME HIERARCHICAL PROTOCOL DECODING [patent_app_type] => utility [patent_app_number] => 16/241192 [patent_app_country] => US [patent_app_date] => 2019-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7817 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16241192 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/241192
Real-time hierarchical protocol decoding Jan 6, 2019 Issued
Array ( [id] => 14689365 [patent_doc_number] => 20190243798 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-08 [patent_title] => APPARATUS FOR VIRTUAL CHANNEL ALLOCATION VIA A HIGH SPEED BUS INTERFACE [patent_app_type] => utility [patent_app_number] => 16/241781 [patent_app_country] => US [patent_app_date] => 2019-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7951 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16241781 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/241781
Apparatus for virtual channel allocation via a high speed bus interface Jan 6, 2019 Issued
Array ( [id] => 16160901 [patent_doc_number] => 20200218683 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-09 [patent_title] => VIRTUALIZATION OF A RECONFIGURABLE DATA PROCESSOR [patent_app_type] => utility [patent_app_number] => 16/239252 [patent_app_country] => US [patent_app_date] => 2019-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19546 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16239252 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/239252
Virtualization of a reconfigurable data processor Jan 2, 2019 Issued
Array ( [id] => 15982445 [patent_doc_number] => 10671550 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-06-02 [patent_title] => Memory offloading a problem using accelerators [patent_app_type] => utility [patent_app_number] => 16/238949 [patent_app_country] => US [patent_app_date] => 2019-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 22 [patent_no_of_words] => 10423 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16238949 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/238949
Memory offloading a problem using accelerators Jan 2, 2019 Issued
Array ( [id] => 15701197 [patent_doc_number] => 10606775 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-03-31 [patent_title] => Computing tile [patent_app_type] => utility [patent_app_number] => 16/236188 [patent_app_country] => US [patent_app_date] => 2018-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10957 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16236188 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/236188
Computing tile Dec 27, 2018 Issued
Array ( [id] => 15545249 [patent_doc_number] => 10572405 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-02-25 [patent_title] => Writing messages in a shared memory architecture for a vehicle [patent_app_type] => utility [patent_app_number] => 16/236182 [patent_app_country] => US [patent_app_date] => 2018-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 21668 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 426 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16236182 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/236182
Writing messages in a shared memory architecture for a vehicle Dec 27, 2018 Issued
Array ( [id] => 14782125 [patent_doc_number] => 20190265960 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-29 [patent_title] => LOGICAL MIGRATION OF APPLICATIONS AND DATA [patent_app_type] => utility [patent_app_number] => 16/227797 [patent_app_country] => US [patent_app_date] => 2018-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5890 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16227797 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/227797
Logical migration of applications and data Dec 19, 2018 Issued
Array ( [id] => 14218521 [patent_doc_number] => 20190121645 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-25 [patent_title] => Instruction And Logic For In-Order Handling In An Out-Of-Order Processor [patent_app_type] => utility [patent_app_number] => 16/225673 [patent_app_country] => US [patent_app_date] => 2018-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20665 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16225673 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/225673
Instruction And Logic For In-Order Handling In An Out-Of-Order Processor Dec 18, 2018 Abandoned
Array ( [id] => 14162095 [patent_doc_number] => 20190108150 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-11 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/213370 [patent_app_country] => US [patent_app_date] => 2018-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5784 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16213370 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/213370
SEMICONDUCTOR DEVICE Dec 6, 2018 Abandoned
Array ( [id] => 15609507 [patent_doc_number] => 10585816 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-03-10 [patent_title] => System and method for serial communication at a peripheral interface device [patent_app_type] => utility [patent_app_number] => 16/213048 [patent_app_country] => US [patent_app_date] => 2018-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 5502 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16213048 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/213048
System and method for serial communication at a peripheral interface device Dec 6, 2018 Issued
Array ( [id] => 14571077 [patent_doc_number] => 20190213145 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-11 [patent_title] => Mobile De-Whitening [patent_app_type] => utility [patent_app_number] => 16/211330 [patent_app_country] => US [patent_app_date] => 2018-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9038 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16211330 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/211330
Mobile de-whitening Dec 5, 2018 Issued
Array ( [id] => 16501532 [patent_doc_number] => 10866917 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-15 [patent_title] => Inter device data exchange via external bus by utilizing communication port [patent_app_type] => utility [patent_app_number] => 16/208369 [patent_app_country] => US [patent_app_date] => 2018-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4544 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16208369 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/208369
Inter device data exchange via external bus by utilizing communication port Dec 2, 2018 Issued
Array ( [id] => 16032615 [patent_doc_number] => 10678728 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-09 [patent_title] => System on chip having semaphore function and method for implementing semaphore function [patent_app_type] => utility [patent_app_number] => 16/192019 [patent_app_country] => US [patent_app_date] => 2018-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 12250 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16192019 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/192019
System on chip having semaphore function and method for implementing semaphore function Nov 14, 2018 Issued
Array ( [id] => 14135567 [patent_doc_number] => 20190102173 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-04 [patent_title] => METHODS AND SYSTEMS FOR TRANSFERRING DATA BETWEEN A PROCESSING DEVICE AND EXTERNAL DEVICES [patent_app_type] => utility [patent_app_number] => 16/190931 [patent_app_country] => US [patent_app_date] => 2018-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 29081 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16190931 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/190931
METHODS AND SYSTEMS FOR TRANSFERRING DATA BETWEEN A PROCESSING DEVICE AND EXTERNAL DEVICES Nov 13, 2018 Abandoned
Array ( [id] => 13961175 [patent_doc_number] => 20190056932 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-21 [patent_title] => Kernel Thread Network Stack Buffering [patent_app_type] => utility [patent_app_number] => 16/166846 [patent_app_country] => US [patent_app_date] => 2018-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6402 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16166846 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/166846
Kernel thread network stack buffering Oct 21, 2018 Issued
Array ( [id] => 16446802 [patent_doc_number] => 10838731 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-17 [patent_title] => Branch prediction based on load-path history [patent_app_type] => utility [patent_app_number] => 16/136151 [patent_app_country] => US [patent_app_date] => 2018-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6413 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16136151 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/136151
Branch prediction based on load-path history Sep 18, 2018 Issued
Array ( [id] => 15653933 [patent_doc_number] => 20200089497 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-19 [patent_title] => INSTRUCTION SET FOR MINIMIZING CONTROL VARIANCE OVERHEAD IN DATAFLOW ARCHITECTURES [patent_app_type] => utility [patent_app_number] => 16/134945 [patent_app_country] => US [patent_app_date] => 2018-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5065 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16134945 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/134945
INSTRUCTION SET FOR MINIMIZING CONTROL VARIANCE OVERHEAD IN DATAFLOW ARCHITECTURES Sep 17, 2018 Abandoned
Array ( [id] => 15653935 [patent_doc_number] => 20200089498 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-19 [patent_title] => USING LOOP EXIT PREDICTION TO ACCELERATE OR SUPPRESS LOOP MODE OF A PROCESSOR [patent_app_type] => utility [patent_app_number] => 16/134440 [patent_app_country] => US [patent_app_date] => 2018-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5783 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16134440 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/134440
Using loop exit prediction to accelerate or suppress loop mode of a processor Sep 17, 2018 Issued
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