Search

Michael Sun

Examiner (ID: 1348, Phone: (571)270-1724 , Office: P/2184 )

Most Active Art Unit
2184
Art Unit(s)
2184, 2183
Total Applications
1016
Issued Applications
892
Pending Applications
48
Abandoned Applications
110

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14668875 [patent_doc_number] => 10372338 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-06 [patent_title] => Memory controller and data processing circuit with improved system efficiency [patent_app_type] => utility [patent_app_number] => 15/868535 [patent_app_country] => US [patent_app_date] => 2018-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5726 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15868535 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/868535
Memory controller and data processing circuit with improved system efficiency Jan 10, 2018 Issued
Array ( [id] => 15106579 [patent_doc_number] => 10474615 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-12 [patent_title] => Hub [patent_app_type] => utility [patent_app_number] => 15/866462 [patent_app_country] => US [patent_app_date] => 2018-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5426 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15866462 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/866462
Hub Jan 9, 2018 Issued
Array ( [id] => 14571119 [patent_doc_number] => 20190213166 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-11 [patent_title] => METHODS AND APPARATUS FOR REDUCED-LATENCY DATA TRANSMISSION WITH AN INTER-PROCESSOR COMMUNICATION LINK BETWEEN INDEPENDENTLY OPERABLE PROCESSORS [patent_app_type] => utility [patent_app_number] => 15/865638 [patent_app_country] => US [patent_app_date] => 2018-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16211 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15865638 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/865638
Methods and apparatus for reduced-latency data transmission with an inter-processor communication link between independently operable processors Jan 8, 2018 Issued
Array ( [id] => 13361569 [patent_doc_number] => 20180232324 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-16 [patent_title] => MULTI-PORT MULTI-SIDEBAND-GPIO CONSOLIDATION TECHNIQUE OVER A MULTI-DROP SERIAL BUS [patent_app_type] => utility [patent_app_number] => 15/864871 [patent_app_country] => US [patent_app_date] => 2018-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13358 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15864871 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/864871
Multi-port multi-sideband-GPIO consolidation technique over a multi-drop serial bus Jan 7, 2018 Issued
Array ( [id] => 15425275 [patent_doc_number] => 10545564 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-28 [patent_title] => Discharge circuit integrated in chip of slave device to follow bus rectifier bridge [patent_app_type] => utility [patent_app_number] => 16/337483 [patent_app_country] => US [patent_app_date] => 2017-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3455 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16337483 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/337483
Discharge circuit integrated in chip of slave device to follow bus rectifier bridge Dec 27, 2017 Issued
Array ( [id] => 13906621 [patent_doc_number] => 20190042515 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-07 [patent_title] => SYSTEM DECODER FOR TRAINING ACCELERATORS [patent_app_type] => utility [patent_app_number] => 15/848218 [patent_app_country] => US [patent_app_date] => 2017-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12993 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15848218 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/848218
System decoder for training accelerators Dec 19, 2017 Issued
Array ( [id] => 12665980 [patent_doc_number] => 20180113826 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-26 [patent_title] => STORAGE APPARATUS ACCESSED BY USING MEMORY BUS [patent_app_type] => utility [patent_app_number] => 15/834016 [patent_app_country] => US [patent_app_date] => 2017-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7343 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15834016 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/834016
Storage apparatus accessed by using memory bus Dec 5, 2017 Issued
Array ( [id] => 14202983 [patent_doc_number] => 10268608 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-23 [patent_title] => Memory module with timing-controlled data paths in distributed data buffers [patent_app_type] => utility [patent_app_number] => 15/820076 [patent_app_country] => US [patent_app_date] => 2017-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 29 [patent_no_of_words] => 11137 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 354 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15820076 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/820076
Memory module with timing-controlled data paths in distributed data buffers Nov 20, 2017 Issued
Array ( [id] => 16171489 [patent_doc_number] => 10713056 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-14 [patent_title] => Wide vector execution in single thread mode for an out-of-order processor [patent_app_type] => utility [patent_app_number] => 15/806419 [patent_app_country] => US [patent_app_date] => 2017-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6191 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15806419 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/806419
Wide vector execution in single thread mode for an out-of-order processor Nov 7, 2017 Issued
Array ( [id] => 13157635 [patent_doc_number] => 10095542 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-09 [patent_title] => Cooperative thread array granularity context switch during trap handling [patent_app_type] => utility [patent_app_number] => 15/798174 [patent_app_country] => US [patent_app_date] => 2017-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10390 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15798174 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/798174
Cooperative thread array granularity context switch during trap handling Oct 29, 2017 Issued
Array ( [id] => 16233234 [patent_doc_number] => 10740787 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-11 [patent_title] => Methods and systems to monitor a media device via a USB port [patent_app_type] => utility [patent_app_number] => 15/789332 [patent_app_country] => US [patent_app_date] => 2017-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10810 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15789332 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/789332
Methods and systems to monitor a media device via a USB port Oct 19, 2017 Issued
Array ( [id] => 14750845 [patent_doc_number] => 20190258596 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-22 [patent_title] => PROVISION OF INFORMATION REGARDING ADDITIONAL FUNCTIONALITIES OF FIELD BUS COMPONENTS [patent_app_type] => utility [patent_app_number] => 16/347218 [patent_app_country] => US [patent_app_date] => 2017-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5701 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16347218 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/347218
Provision of information regarding additional functionalities of field bus components Oct 9, 2017 Issued
Array ( [id] => 14149703 [patent_doc_number] => 10255232 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-09 [patent_title] => Computer architecture with a hardware accumulator reset [patent_app_type] => utility [patent_app_number] => 15/726410 [patent_app_country] => US [patent_app_date] => 2017-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 6506 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15726410 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/726410
Computer architecture with a hardware accumulator reset Oct 5, 2017 Issued
Array ( [id] => 14135873 [patent_doc_number] => 20190102326 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-04 [patent_title] => METHOD, APPARATUS, SYSTEM FOR EARLY PAGE GRANULAR HINTS FROM A PCIE DEVICE [patent_app_type] => utility [patent_app_number] => 15/721777 [patent_app_country] => US [patent_app_date] => 2017-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11803 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15721777 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/721777
Method, apparatus, system for early page granular hints from a PCIe device Sep 29, 2017 Issued
Array ( [id] => 14555529 [patent_doc_number] => 10346226 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-09 [patent_title] => Methods and apparatus for transmitting time sensitive data over a tunneled bus interface [patent_app_type] => utility [patent_app_number] => 15/720603 [patent_app_country] => US [patent_app_date] => 2017-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9125 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15720603 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/720603
Methods and apparatus for transmitting time sensitive data over a tunneled bus interface Sep 28, 2017 Issued
Array ( [id] => 14110275 [patent_doc_number] => 20190096813 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-28 [patent_title] => INTEGRATION OF A PROGRAMMABLE DEVICE AND A PROCESSING SYSTEM IN AN INTEGRATED CIRCUIT PACKAGE [patent_app_type] => utility [patent_app_number] => 15/719288 [patent_app_country] => US [patent_app_date] => 2017-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10380 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15719288 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/719288
Integration of a programmable device and a processing system in an integrated circuit package Sep 27, 2017 Issued
Array ( [id] => 14107387 [patent_doc_number] => 20190095369 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-28 [patent_title] => PROCESSORS, METHODS, AND SYSTEMS FOR A MEMORY FENCE IN A CONFIGURABLE SPATIAL ACCELERATOR [patent_app_type] => utility [patent_app_number] => 15/719285 [patent_app_country] => US [patent_app_date] => 2017-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 43438 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15719285 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/719285
Processors, methods, and systems for a memory fence in a configurable spatial accelerator Sep 27, 2017 Issued
Array ( [id] => 12140210 [patent_doc_number] => 20180018293 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-18 [patent_title] => 'METHOD, CONTROLLER, AND SYSTEM FOR SERVICE FLOW CONTROL IN OBJECT-BASED STORAGE SYSTEM' [patent_app_type] => utility [patent_app_number] => 15/716163 [patent_app_country] => US [patent_app_date] => 2017-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 26285 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15716163 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/716163
Method, controller, and system for service flow control in object-based storage system Sep 25, 2017 Issued
Array ( [id] => 16065073 [patent_doc_number] => 10691486 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-23 [patent_title] => Processor comprising a plurality of computation cores [patent_app_type] => utility [patent_app_number] => 15/714704 [patent_app_country] => US [patent_app_date] => 2017-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3424 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15714704 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/714704
Processor comprising a plurality of computation cores Sep 24, 2017 Issued
Array ( [id] => 12570855 [patent_doc_number] => 10019201 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-07-10 [patent_title] => Reservations over multiple paths over fabrics [patent_app_type] => utility [patent_app_number] => 15/667529 [patent_app_country] => US [patent_app_date] => 2017-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 15903 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15667529 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/667529
Reservations over multiple paths over fabrics Aug 1, 2017 Issued
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