Search

Michael Sun

Examiner (ID: 1348, Phone: (571)270-1724 , Office: P/2184 )

Most Active Art Unit
2184
Art Unit(s)
2184, 2183
Total Applications
1016
Issued Applications
892
Pending Applications
48
Abandoned Applications
110

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16145553 [patent_doc_number] => 10705847 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-07 [patent_title] => Wide vector execution in single thread mode for an out-of-order processor [patent_app_type] => utility [patent_app_number] => 15/665653 [patent_app_country] => US [patent_app_date] => 2017-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6167 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15665653 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/665653
Wide vector execution in single thread mode for an out-of-order processor Jul 31, 2017 Issued
Array ( [id] => 16037311 [patent_doc_number] => 10681097 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-09 [patent_title] => Methods and systems for data transmission [patent_app_type] => utility [patent_app_number] => 15/649456 [patent_app_country] => US [patent_app_date] => 2017-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 34 [patent_no_of_words] => 19109 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15649456 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/649456
Methods and systems for data transmission Jul 12, 2017 Issued
Array ( [id] => 15043117 [patent_doc_number] => 20190332563 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-31 [patent_title] => PLUG CONNECTOR COMPONENT, PLUG CONNECTOR, PLUG CONNECTOR SYSTEM AND METHOD FOR ASSEMBLING AND OPERATING A PLUG CONNECTOR [patent_app_type] => utility [patent_app_number] => 16/310156 [patent_app_country] => US [patent_app_date] => 2017-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6531 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16310156 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/310156
Plug connector component, plug connector, plug connector system and method for assembling and operating a plug connector Jul 6, 2017 Issued
Array ( [id] => 17499362 [patent_doc_number] => 11288068 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-29 [patent_title] => Systems, methods, and apparatus for matrix move [patent_app_type] => utility [patent_app_number] => 16/487747 [patent_app_country] => US [patent_app_date] => 2017-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 44 [patent_no_of_words] => 19544 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16487747 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/487747
Systems, methods, and apparatus for matrix move Jun 30, 2017 Issued
Array ( [id] => 17016984 [patent_doc_number] => 11086623 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-10 [patent_title] => Systems, methods, and apparatuses for tile matrix multiplication and accumulation [patent_app_type] => utility [patent_app_number] => 16/487787 [patent_app_country] => US [patent_app_date] => 2017-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 47 [patent_no_of_words] => 21338 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16487787 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/487787
Systems, methods, and apparatuses for tile matrix multiplication and accumulation Jun 30, 2017 Issued
Array ( [id] => 16418807 [patent_doc_number] => 10826720 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-03 [patent_title] => Switching device and determination method [patent_app_type] => utility [patent_app_number] => 16/337160 [patent_app_country] => US [patent_app_date] => 2017-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9832 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16337160 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/337160
Switching device and determination method Jun 27, 2017 Issued
Array ( [id] => 11982043 [patent_doc_number] => 20170286196 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-05 [patent_title] => 'Processing System With Interspersed Processors With Multi-Layer Interconnection' [patent_app_type] => utility [patent_app_number] => 15/631925 [patent_app_country] => US [patent_app_date] => 2017-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 20153 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15631925 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/631925
Processing system with interspersed processors with multi-layer interconnection Jun 22, 2017 Issued
Array ( [id] => 12229035 [patent_doc_number] => 09916281 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-13 [patent_title] => 'Processing system with a secure set of executable instructions and/or addressing scheme' [patent_app_type] => utility [patent_app_number] => 15/600006 [patent_app_country] => US [patent_app_date] => 2017-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 6116 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15600006 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/600006
Processing system with a secure set of executable instructions and/or addressing scheme May 18, 2017 Issued
Array ( [id] => 12413970 [patent_doc_number] => 09971599 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-15 [patent_title] => Instruction and logic for support of code modification [patent_app_type] => utility [patent_app_number] => 15/589445 [patent_app_country] => US [patent_app_date] => 2017-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 33 [patent_no_of_words] => 23695 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15589445 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/589445
Instruction and logic for support of code modification May 7, 2017 Issued
Array ( [id] => 12688642 [patent_doc_number] => 20180121380 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-03 [patent_title] => System Arbiter with Programmable Priority Levels [patent_app_type] => utility [patent_app_number] => 15/498846 [patent_app_country] => US [patent_app_date] => 2017-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2428 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15498846 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/498846
System arbiter with programmable priority levels Apr 26, 2017 Issued
Array ( [id] => 13526031 [patent_doc_number] => 20180314558 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-01 [patent_title] => SYSTEMS AND METHODS FOR SCALABLE CLOUD COMPUTING BY OPTIMALLY UTILIZING MANAGEMENT CONTROLLER FOR HOST COMPUTE PROCESSING [patent_app_type] => utility [patent_app_number] => 15/497481 [patent_app_country] => US [patent_app_date] => 2017-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3747 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15497481 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/497481
Systems and methods for scalable cloud computing by optimally utilizing management controller for host compute processing Apr 25, 2017 Issued
Array ( [id] => 14798439 [patent_doc_number] => 10402223 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-09-03 [patent_title] => Scheduling hardware resources for offloading functions in a heterogeneous computing system [patent_app_type] => utility [patent_app_number] => 15/498226 [patent_app_country] => US [patent_app_date] => 2017-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 10423 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15498226 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/498226
Scheduling hardware resources for offloading functions in a heterogeneous computing system Apr 25, 2017 Issued
Array ( [id] => 14175389 [patent_doc_number] => 10261708 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-04-16 [patent_title] => Host data replication allocating single memory buffers to store multiple buffers of received host data and to internally process the received host data [patent_app_type] => utility [patent_app_number] => 15/497804 [patent_app_country] => US [patent_app_date] => 2017-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7956 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15497804 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/497804
Host data replication allocating single memory buffers to store multiple buffers of received host data and to internally process the received host data Apr 25, 2017 Issued
Array ( [id] => 12053389 [patent_doc_number] => 20170329733 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-16 [patent_title] => 'MULTI-HOST SUPPORTED UNIVERSAL SERIAL BUS HUB AND AUTOMOBILE HEAD UNIT USING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/496645 [patent_app_country] => US [patent_app_date] => 2017-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5385 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15496645 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/496645
Multi-host supported universal serial bus hub and automobile head unit using the same Apr 24, 2017 Issued
Array ( [id] => 14614689 [patent_doc_number] => 10360045 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-23 [patent_title] => Event-driven schemes for determining suspend/resume periods [patent_app_type] => utility [patent_app_number] => 15/496490 [patent_app_country] => US [patent_app_date] => 2017-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 13783 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15496490 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/496490
Event-driven schemes for determining suspend/resume periods Apr 24, 2017 Issued
Array ( [id] => 12011663 [patent_doc_number] => 09804981 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-31 [patent_title] => 'Method, controller, and system for service flow control in object-based storage system' [patent_app_type] => utility [patent_app_number] => 15/490118 [patent_app_country] => US [patent_app_date] => 2017-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 26271 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15490118 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/490118
Method, controller, and system for service flow control in object-based storage system Apr 17, 2017 Issued
Array ( [id] => 14523333 [patent_doc_number] => 10338927 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-02 [patent_title] => Method and apparatus for implementing a dynamic out-of-order processor pipeline [patent_app_type] => utility [patent_app_number] => 15/477374 [patent_app_country] => US [patent_app_date] => 2017-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 22 [patent_no_of_words] => 14583 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15477374 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/477374
Method and apparatus for implementing a dynamic out-of-order processor pipeline Apr 2, 2017 Issued
Array ( [id] => 14107067 [patent_doc_number] => 20190095209 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-28 [patent_title] => PROGRAM LOOP CONTROL [patent_app_type] => utility [patent_app_number] => 16/080736 [patent_app_country] => US [patent_app_date] => 2017-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16290 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16080736 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/080736
Program loop control Mar 20, 2017 Issued
Array ( [id] => 11965919 [patent_doc_number] => 20170270072 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-21 [patent_title] => 'BLADE TEST ACCESS MATRIX' [patent_app_type] => utility [patent_app_number] => 15/461757 [patent_app_country] => US [patent_app_date] => 2017-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 8942 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15461757 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/461757
BLADE TEST ACCESS MATRIX Mar 16, 2017 Abandoned
Array ( [id] => 13432765 [patent_doc_number] => 20180267925 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-20 [patent_title] => Distributed Logic Control Apparatus [patent_app_type] => utility [patent_app_number] => 15/461699 [patent_app_country] => US [patent_app_date] => 2017-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9216 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15461699 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/461699
Distributed logic control apparatus Mar 16, 2017 Issued
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