Search

Michael Sun

Examiner (ID: 11045, Phone: (571)270-1724 , Office: P/2184 )

Most Active Art Unit
2184
Art Unit(s)
2184, 2183
Total Applications
1032
Issued Applications
904
Pending Applications
48
Abandoned Applications
110

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14798439 [patent_doc_number] => 10402223 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-09-03 [patent_title] => Scheduling hardware resources for offloading functions in a heterogeneous computing system [patent_app_type] => utility [patent_app_number] => 15/498226 [patent_app_country] => US [patent_app_date] => 2017-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 10423 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15498226 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/498226
Scheduling hardware resources for offloading functions in a heterogeneous computing system Apr 25, 2017 Issued
Array ( [id] => 14175389 [patent_doc_number] => 10261708 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-04-16 [patent_title] => Host data replication allocating single memory buffers to store multiple buffers of received host data and to internally process the received host data [patent_app_type] => utility [patent_app_number] => 15/497804 [patent_app_country] => US [patent_app_date] => 2017-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7956 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15497804 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/497804
Host data replication allocating single memory buffers to store multiple buffers of received host data and to internally process the received host data Apr 25, 2017 Issued
Array ( [id] => 13526031 [patent_doc_number] => 20180314558 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-01 [patent_title] => SYSTEMS AND METHODS FOR SCALABLE CLOUD COMPUTING BY OPTIMALLY UTILIZING MANAGEMENT CONTROLLER FOR HOST COMPUTE PROCESSING [patent_app_type] => utility [patent_app_number] => 15/497481 [patent_app_country] => US [patent_app_date] => 2017-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3747 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15497481 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/497481
Systems and methods for scalable cloud computing by optimally utilizing management controller for host compute processing Apr 25, 2017 Issued
Array ( [id] => 14614689 [patent_doc_number] => 10360045 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-23 [patent_title] => Event-driven schemes for determining suspend/resume periods [patent_app_type] => utility [patent_app_number] => 15/496490 [patent_app_country] => US [patent_app_date] => 2017-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 13783 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15496490 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/496490
Event-driven schemes for determining suspend/resume periods Apr 24, 2017 Issued
Array ( [id] => 12053389 [patent_doc_number] => 20170329733 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-16 [patent_title] => 'MULTI-HOST SUPPORTED UNIVERSAL SERIAL BUS HUB AND AUTOMOBILE HEAD UNIT USING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/496645 [patent_app_country] => US [patent_app_date] => 2017-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5385 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15496645 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/496645
Multi-host supported universal serial bus hub and automobile head unit using the same Apr 24, 2017 Issued
Array ( [id] => 12011663 [patent_doc_number] => 09804981 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-31 [patent_title] => 'Method, controller, and system for service flow control in object-based storage system' [patent_app_type] => utility [patent_app_number] => 15/490118 [patent_app_country] => US [patent_app_date] => 2017-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 26271 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15490118 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/490118
Method, controller, and system for service flow control in object-based storage system Apr 17, 2017 Issued
Array ( [id] => 14523333 [patent_doc_number] => 10338927 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-02 [patent_title] => Method and apparatus for implementing a dynamic out-of-order processor pipeline [patent_app_type] => utility [patent_app_number] => 15/477374 [patent_app_country] => US [patent_app_date] => 2017-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 22 [patent_no_of_words] => 14583 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15477374 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/477374
Method and apparatus for implementing a dynamic out-of-order processor pipeline Apr 2, 2017 Issued
Array ( [id] => 14107067 [patent_doc_number] => 20190095209 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-28 [patent_title] => PROGRAM LOOP CONTROL [patent_app_type] => utility [patent_app_number] => 16/080736 [patent_app_country] => US [patent_app_date] => 2017-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16290 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16080736 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/080736
Program loop control Mar 20, 2017 Issued
Array ( [id] => 11965919 [patent_doc_number] => 20170270072 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-21 [patent_title] => 'BLADE TEST ACCESS MATRIX' [patent_app_type] => utility [patent_app_number] => 15/461757 [patent_app_country] => US [patent_app_date] => 2017-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 8942 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15461757 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/461757
BLADE TEST ACCESS MATRIX Mar 16, 2017 Abandoned
Array ( [id] => 13432765 [patent_doc_number] => 20180267925 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-20 [patent_title] => Distributed Logic Control Apparatus [patent_app_type] => utility [patent_app_number] => 15/461699 [patent_app_country] => US [patent_app_date] => 2017-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9216 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15461699 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/461699
Distributed logic control apparatus Mar 16, 2017 Issued
Array ( [id] => 13948699 [patent_doc_number] => 10210125 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-19 [patent_title] => Receive queue with stride-based data scattering [patent_app_type] => utility [patent_app_number] => 15/460251 [patent_app_country] => US [patent_app_date] => 2017-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 7293 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15460251 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/460251
Receive queue with stride-based data scattering Mar 15, 2017 Issued
Array ( [id] => 16910337 [patent_doc_number] => 11042376 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-22 [patent_title] => Method of allocating a virtual register stack in a stack machine [patent_app_type] => utility [patent_app_number] => 16/079628 [patent_app_country] => US [patent_app_date] => 2017-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1910 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16079628 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/079628
Method of allocating a virtual register stack in a stack machine Feb 26, 2017 Issued
Array ( [id] => 15982135 [patent_doc_number] => 10671395 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-02 [patent_title] => Application specific instruction-set processor (ASIP) for simultaneously executing a plurality of operations using a long instruction word [patent_app_type] => utility [patent_app_number] => 15/431493 [patent_app_country] => US [patent_app_date] => 2017-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5339 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15431493 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/431493
Application specific instruction-set processor (ASIP) for simultaneously executing a plurality of operations using a long instruction word Feb 12, 2017 Issued
Array ( [id] => 15198201 [patent_doc_number] => 10496596 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-03 [patent_title] => Application specific instruction-set processor (ASIP) architecture having separated input and output data ports [patent_app_type] => utility [patent_app_number] => 15/431394 [patent_app_country] => US [patent_app_date] => 2017-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4055 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15431394 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/431394
Application specific instruction-set processor (ASIP) architecture having separated input and output data ports Feb 12, 2017 Issued
Array ( [id] => 13347159 [patent_doc_number] => 20180225119 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-09 [patent_title] => INFINITE PROCESSOR THREAD BALANCING [patent_app_type] => utility [patent_app_number] => 15/428441 [patent_app_country] => US [patent_app_date] => 2017-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6653 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15428441 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/428441
Infinite processor thread balancing Feb 8, 2017 Issued
Array ( [id] => 13281481 [patent_doc_number] => 10152325 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-11 [patent_title] => Instruction and logic to provide pushing buffer copy and store functionality [patent_app_type] => utility [patent_app_number] => 15/426963 [patent_app_country] => US [patent_app_date] => 2017-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 28 [patent_no_of_words] => 18007 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15426963 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/426963
Instruction and logic to provide pushing buffer copy and store functionality Feb 6, 2017 Issued
Array ( [id] => 11651613 [patent_doc_number] => 20170147514 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-25 [patent_title] => 'MEMORY MODULE WITH TIMING-CONTROLLED DATA PATHS IN DISTRIBUTED DATA BUFFERS' [patent_app_type] => utility [patent_app_number] => 15/426064 [patent_app_country] => US [patent_app_date] => 2017-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 11612 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15426064 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/426064
Memory module with timing-controlled data paths in distributed data buffers Feb 6, 2017 Issued
Array ( [id] => 11875269 [patent_doc_number] => 09747039 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-08-29 [patent_title] => 'Reservations over multiple paths on NVMe over fabrics' [patent_app_type] => utility [patent_app_number] => 15/419886 [patent_app_country] => US [patent_app_date] => 2017-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 17017 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15419886 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/419886
Reservations over multiple paths on NVMe over fabrics Jan 29, 2017 Issued
Array ( [id] => 14298945 [patent_doc_number] => 10289599 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-14 [patent_title] => System and method employed for signal reception by providing programmable and switchable line terminations [patent_app_type] => utility [patent_app_number] => 15/404217 [patent_app_country] => US [patent_app_date] => 2017-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2369 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15404217 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/404217
System and method employed for signal reception by providing programmable and switchable line terminations Jan 11, 2017 Issued
Array ( [id] => 13752653 [patent_doc_number] => 10169273 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-01 [patent_title] => Forced compression of single I2C writes [patent_app_type] => utility [patent_app_number] => 15/403559 [patent_app_country] => US [patent_app_date] => 2017-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 12113 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15403559 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/403559
Forced compression of single I2C writes Jan 10, 2017 Issued
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