
Michael Sun
Examiner (ID: 11045, Phone: (571)270-1724 , Office: P/2184 )
| Most Active Art Unit | 2184 |
| Art Unit(s) | 2184, 2183 |
| Total Applications | 1032 |
| Issued Applications | 904 |
| Pending Applications | 48 |
| Abandoned Applications | 110 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 10680441
[patent_doc_number] => 20160026585
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-01-28
[patent_title] => 'VALIDATING CONNECTION, STRUCTURAL CHARACTERISTICS AND POSITIONING OF CABLE CONNECTORS'
[patent_app_type] => utility
[patent_app_number] => 14/877397
[patent_app_country] => US
[patent_app_date] => 2015-10-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 9702
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14877397
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/877397 | Validating connection, structural characteristics and positioning of cable connectors | Oct 6, 2015 | Issued |
Array
(
[id] => 11544085
[patent_doc_number] => 20170097910
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-04-06
[patent_title] => 'DIRECT MEMORY ACCESS FOR PROGRAMMABLE LOGIC DEVICE CONFIGURATION'
[patent_app_type] => utility
[patent_app_number] => 14/876467
[patent_app_country] => US
[patent_app_date] => 2015-10-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5437
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14876467
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/876467 | Direct memory access for programmable logic device configuration | Oct 5, 2015 | Issued |
Array
(
[id] => 12895471
[patent_doc_number] => 20180190332
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-07-05
[patent_title] => EFFICIENT MEMORY ACTIVATION AT RUNTIME
[patent_app_type] => utility
[patent_app_number] => 15/755469
[patent_app_country] => US
[patent_app_date] => 2015-09-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7019
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -22
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15755469
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/755469 | Efficient memory activation at runtime | Sep 24, 2015 | Issued |
Array
(
[id] => 13157831
[patent_doc_number] => 10095641
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-10-09
[patent_title] => Processor with frames/bins structure in local high speed memory
[patent_app_type] => utility
[patent_app_number] => 14/863032
[patent_app_country] => US
[patent_app_date] => 2015-09-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 27
[patent_no_of_words] => 39746
[patent_no_of_claims] => 40
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 403
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14863032
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/863032 | Processor with frames/bins structure in local high speed memory | Sep 22, 2015 | Issued |
Array
(
[id] => 10739571
[patent_doc_number] => 20160085722
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-03-24
[patent_title] => 'DATA PACKET PROCESSING'
[patent_app_type] => utility
[patent_app_number] => 14/862599
[patent_app_country] => US
[patent_app_date] => 2015-09-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 8538
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14862599
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/862599 | Data packet processing | Sep 22, 2015 | Issued |
Array
(
[id] => 10665853
[patent_doc_number] => 20160011998
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-01-14
[patent_title] => 'DIRECT MEMORY ACCESS CONTROLLER'
[patent_app_type] => utility
[patent_app_number] => 14/860398
[patent_app_country] => US
[patent_app_date] => 2015-09-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 10410
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14860398
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/860398 | Direct memory access controller | Sep 20, 2015 | Issued |
Array
(
[id] => 10688263
[patent_doc_number] => 20160034408
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-02-04
[patent_title] => 'MEMORY MODULE WITH DISTRIBUTED DATA BUFFERS AND METHOD OF OPERATION'
[patent_app_type] => utility
[patent_app_number] => 14/846993
[patent_app_country] => US
[patent_app_date] => 2015-09-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
[patent_figures_cnt] => 27
[patent_no_of_words] => 11610
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14846993
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/846993 | Memory module with distributed data buffers and method of operation | Sep 6, 2015 | Issued |
Array
(
[id] => 10746065
[patent_doc_number] => 20160092216
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-03-31
[patent_title] => 'OPTIMIZING GROUPING OF INSTRUCTIONS'
[patent_app_type] => utility
[patent_app_number] => 14/841805
[patent_app_country] => US
[patent_app_date] => 2015-09-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5415
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14841805
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/841805 | Optimizing grouping of instructions | Aug 31, 2015 | Issued |
Array
(
[id] => 13948587
[patent_doc_number] => 10210069
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-02-19
[patent_title] => Real-time hierarchical protocol decoding
[patent_app_type] => utility
[patent_app_number] => 14/841130
[patent_app_country] => US
[patent_app_date] => 2015-08-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 22
[patent_no_of_words] => 7792
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14841130
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/841130 | Real-time hierarchical protocol decoding | Aug 30, 2015 | Issued |
Array
(
[id] => 10466628
[patent_doc_number] => 20150351643
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-12-10
[patent_title] => 'CONFIGURABLE HEALTH-CARE EQUIPMENT APPARATUS'
[patent_app_type] => utility
[patent_app_number] => 14/831618
[patent_app_country] => US
[patent_app_date] => 2015-08-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 54
[patent_figures_cnt] => 54
[patent_no_of_words] => 19213
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14831618
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/831618 | Configurable health-care equipment apparatus | Aug 19, 2015 | Issued |
Array
(
[id] => 10746074
[patent_doc_number] => 20160092225
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-03-31
[patent_title] => 'CHECKPOINTS FOR A SIMULTANEOUS MULTITHREADING PROCESSOR'
[patent_app_type] => utility
[patent_app_number] => 14/830804
[patent_app_country] => US
[patent_app_date] => 2015-08-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 8157
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14830804
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/830804 | Checkpoints for a simultaneous multithreading processor | Aug 19, 2015 | Issued |
Array
(
[id] => 11452001
[patent_doc_number] => 09575640
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-02-21
[patent_title] => 'System for storage and navigation of application states and interactions'
[patent_app_type] => utility
[patent_app_number] => 14/830086
[patent_app_country] => US
[patent_app_date] => 2015-08-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 24
[patent_no_of_words] => 20981
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 234
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14830086
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/830086 | System for storage and navigation of application states and interactions | Aug 18, 2015 | Issued |
Array
(
[id] => 12352449
[patent_doc_number] => 09952992
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-04-24
[patent_title] => Transaction request optimization for redirected USB devices over a network
[patent_app_type] => utility
[patent_app_number] => 14/813252
[patent_app_country] => US
[patent_app_date] => 2015-07-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 7174
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 154
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14813252
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/813252 | Transaction request optimization for redirected USB devices over a network | Jul 29, 2015 | Issued |
Array
(
[id] => 12256048
[patent_doc_number] => 09928191
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-03-27
[patent_title] => 'Communication device with selective encoding'
[patent_app_type] => utility
[patent_app_number] => 14/813621
[patent_app_country] => US
[patent_app_date] => 2015-07-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 6958
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14813621
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/813621 | Communication device with selective encoding | Jul 29, 2015 | Issued |
Array
(
[id] => 11614342
[patent_doc_number] => 09652198
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-05-16
[patent_title] => 'FIFO buffer clean-up'
[patent_app_type] => utility
[patent_app_number] => 14/812933
[patent_app_country] => US
[patent_app_date] => 2015-07-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 13
[patent_no_of_words] => 4411
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14812933
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/812933 | FIFO buffer clean-up | Jul 28, 2015 | Issued |
Array
(
[id] => 12297072
[patent_doc_number] => 09936049
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-04-03
[patent_title] => Protocol independent way for dynamically selecting data compression methods for redirected USB devices
[patent_app_type] => utility
[patent_app_number] => 14/812572
[patent_app_country] => US
[patent_app_date] => 2015-07-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 7040
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14812572
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/812572 | Protocol independent way for dynamically selecting data compression methods for redirected USB devices | Jul 28, 2015 | Issued |
Array
(
[id] => 12201585
[patent_doc_number] => 09904651
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-02-27
[patent_title] => 'Operating method of controller for setting link between interfaces of electronic devices, and storage device including controller'
[patent_app_type] => utility
[patent_app_number] => 14/812318
[patent_app_country] => US
[patent_app_date] => 2015-07-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 20715
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 175
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14812318
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/812318 | Operating method of controller for setting link between interfaces of electronic devices, and storage device including controller | Jul 28, 2015 | Issued |
Array
(
[id] => 13129227
[patent_doc_number] => 10082541
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-09-25
[patent_title] => Mixed redundancy scheme for inter-die interconnects in a multichip package
[patent_app_type] => utility
[patent_app_number] => 14/737246
[patent_app_country] => US
[patent_app_date] => 2015-06-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 5682
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 77
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14737246
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/737246 | Mixed redundancy scheme for inter-die interconnects in a multichip package | Jun 10, 2015 | Issued |
Array
(
[id] => 13129227
[patent_doc_number] => 10082541
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-09-25
[patent_title] => Mixed redundancy scheme for inter-die interconnects in a multichip package
[patent_app_type] => utility
[patent_app_number] => 14/737246
[patent_app_country] => US
[patent_app_date] => 2015-06-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 5682
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 77
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14737246
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/737246 | Mixed redundancy scheme for inter-die interconnects in a multichip package | Jun 10, 2015 | Issued |
Array
(
[id] => 13129227
[patent_doc_number] => 10082541
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-09-25
[patent_title] => Mixed redundancy scheme for inter-die interconnects in a multichip package
[patent_app_type] => utility
[patent_app_number] => 14/737246
[patent_app_country] => US
[patent_app_date] => 2015-06-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 5682
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 77
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14737246
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/737246 | Mixed redundancy scheme for inter-die interconnects in a multichip package | Jun 10, 2015 | Issued |