Search

Michael Sun

Examiner (ID: 1348, Phone: (571)270-1724 , Office: P/2184 )

Most Active Art Unit
2184
Art Unit(s)
2184, 2183
Total Applications
1016
Issued Applications
892
Pending Applications
48
Abandoned Applications
110

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10658292 [patent_doc_number] => 20160004436 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-07 [patent_title] => 'HOST CONTROLLER' [patent_app_type] => utility [patent_app_number] => 14/718461 [patent_app_country] => US [patent_app_date] => 2015-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6222 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14718461 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/718461
Host controller May 20, 2015 Issued
Array ( [id] => 11606711 [patent_doc_number] => 20170124014 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-04 [patent_title] => 'ASIC CHIP SYSTEM DEDICATED FOR OPTICAL THREE-DIMENSIONAL SENSING' [patent_app_type] => utility [patent_app_number] => 15/321928 [patent_app_country] => US [patent_app_date] => 2015-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4347 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15321928 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/321928
ASIC chip system dedicated for optical three-dimensional sensing May 20, 2015 Issued
Array ( [id] => 10363238 [patent_doc_number] => 20150248243 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-03 [patent_title] => 'SELF-DETECTING STORAGE BOTTLENECK WHILE HANDLING SEQUENTIAL I/O OPERATIONS' [patent_app_type] => utility [patent_app_number] => 14/712657 [patent_app_country] => US [patent_app_date] => 2015-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6339 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14712657 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/712657
Self-detecting storage bottleneck while handling sequential I/O operations May 13, 2015 Issued
Array ( [id] => 14952993 [patent_doc_number] => 10437761 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-08 [patent_title] => Universal serial bus management [patent_app_type] => utility [patent_app_number] => 15/544673 [patent_app_country] => US [patent_app_date] => 2015-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2874 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15544673 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/544673
Universal serial bus management Apr 16, 2015 Issued
Array ( [id] => 10536738 [patent_doc_number] => 09262369 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-02-16 [patent_title] => 'Apparatus and method for accelerated page link list processing in a packet processor operating at wirespeed' [patent_app_type] => utility [patent_app_number] => 14/676791 [patent_app_country] => US [patent_app_date] => 2015-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3851 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14676791 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/676791
Apparatus and method for accelerated page link list processing in a packet processor operating at wirespeed Mar 31, 2015 Issued
Array ( [id] => 11646084 [patent_doc_number] => 09667487 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-30 [patent_title] => 'Method and apparatus for changing input type in input system using universal plug and play' [patent_app_type] => utility [patent_app_number] => 14/673075 [patent_app_country] => US [patent_app_date] => 2015-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4241 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14673075 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/673075
Method and apparatus for changing input type in input system using universal plug and play Mar 29, 2015 Issued
Array ( [id] => 10293228 [patent_doc_number] => 20150178227 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-25 [patent_title] => 'COOPERATION OF DEVICE AND DISPLAY' [patent_app_type] => utility [patent_app_number] => 14/634318 [patent_app_country] => US [patent_app_date] => 2015-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 11390 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14634318 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/634318
Cooperation of device and display Feb 26, 2015 Issued
Array ( [id] => 12128226 [patent_doc_number] => 20180011812 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-11 [patent_title] => 'INFORMATION PROCESSING APPARATUS' [patent_app_type] => utility [patent_app_number] => 15/545461 [patent_app_country] => US [patent_app_date] => 2015-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 13709 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15545461 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/545461
Information processing apparatus Feb 24, 2015 Issued
Array ( [id] => 12128131 [patent_doc_number] => 20180011717 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-11 [patent_title] => 'MANAGEMENT SYSTEM AND MANAGEMENT METHOD FOR COMPONENT MOUNTING LINE' [patent_app_type] => utility [patent_app_number] => 15/550064 [patent_app_country] => US [patent_app_date] => 2015-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6299 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15550064 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/550064
Management system and management method for component mounting line Feb 12, 2015 Issued
Array ( [id] => 11777267 [patent_doc_number] => 09386264 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-07-05 [patent_title] => 'Augmenting capabilities of a host device' [patent_app_type] => utility [patent_app_number] => 14/614366 [patent_app_country] => US [patent_app_date] => 2015-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 7411 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14614366 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/614366
Augmenting capabilities of a host device Feb 3, 2015 Issued
Array ( [id] => 10228530 [patent_doc_number] => 20150113523 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-23 [patent_title] => 'LOGICAL MIGRATION OF APPLICATIONS AND DATA' [patent_app_type] => utility [patent_app_number] => 14/579621 [patent_app_country] => US [patent_app_date] => 2014-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6096 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14579621 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/579621
Logical migration of applications and data Dec 21, 2014 Issued
Array ( [id] => 10153510 [patent_doc_number] => 09185823 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-11-10 [patent_title] => 'Hybrid memory blade' [patent_app_type] => utility [patent_app_number] => 14/576008 [patent_app_country] => US [patent_app_date] => 2014-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5273 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14576008 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/576008
Hybrid memory blade Dec 17, 2014 Issued
Array ( [id] => 10824750 [patent_doc_number] => 20160170916 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-16 [patent_title] => 'COHERENT MEMORY INTERLEAVING WITH UNIFORM LATENCY' [patent_app_type] => utility [patent_app_number] => 14/568433 [patent_app_country] => US [patent_app_date] => 2014-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4105 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14568433 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/568433
Coherent memory interleaving with uniform latency Dec 11, 2014 Issued
Array ( [id] => 10824761 [patent_doc_number] => 20160170927 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-16 [patent_title] => 'ACCESS AND PROTECTION OF I2C INTERFACES' [patent_app_type] => utility [patent_app_number] => 14/568524 [patent_app_country] => US [patent_app_date] => 2014-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5037 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14568524 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/568524
Access and protection of I2C interfaces Dec 11, 2014 Issued
Array ( [id] => 12194701 [patent_doc_number] => 09898432 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-20 [patent_title] => 'Data transfer control apparatus' [patent_app_type] => utility [patent_app_number] => 14/567287 [patent_app_country] => US [patent_app_date] => 2014-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7445 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14567287 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/567287
Data transfer control apparatus Dec 10, 2014 Issued
Array ( [id] => 12194704 [patent_doc_number] => 09898435 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-20 [patent_title] => 'Aggregate baseboard management controller (BMC) controller' [patent_app_type] => utility [patent_app_number] => 14/566468 [patent_app_country] => US [patent_app_date] => 2014-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6780 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14566468 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/566468
Aggregate baseboard management controller (BMC) controller Dec 9, 2014 Issued
Array ( [id] => 10320745 [patent_doc_number] => 20150205749 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-23 [patent_title] => 'METHODS AND APPARATUS FOR VIRTUAL CHANNEL ALLOCATION VIA A HIGH SPEED BUS INTERFACE' [patent_app_type] => utility [patent_app_number] => 14/566454 [patent_app_country] => US [patent_app_date] => 2014-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8117 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14566454 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/566454
Methods and apparatus for virtual channel allocation via a high speed bus interface Dec 9, 2014 Issued
Array ( [id] => 13240993 [patent_doc_number] => 10133695 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-20 [patent_title] => Link system for establishing high speed network communications and file transfer between hosts using I/O device links [patent_app_type] => utility [patent_app_number] => 14/917402 [patent_app_country] => US [patent_app_date] => 2014-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 19446 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14917402 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/917402
Link system for establishing high speed network communications and file transfer between hosts using I/O device links Dec 7, 2014 Issued
Array ( [id] => 11816911 [patent_doc_number] => 09720861 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-01 [patent_title] => 'Memory access by dual processor systems' [patent_app_type] => utility [patent_app_number] => 14/558147 [patent_app_country] => US [patent_app_date] => 2014-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2666 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14558147 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/558147
Memory access by dual processor systems Dec 1, 2014 Issued
Array ( [id] => 10293174 [patent_doc_number] => 20150178173 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-25 [patent_title] => 'VALIDATING CONNECTION, STRUCTURAL CHARACTERISTICS AND POSITIONING OF CABLE CONNECTORS' [patent_app_type] => utility [patent_app_number] => 14/555824 [patent_app_country] => US [patent_app_date] => 2014-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9720 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14555824 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/555824
Validating connection, structural characteristics and positioning of cable connectors Nov 27, 2014 Issued
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