Search

Michael Sun

Examiner (ID: 11045, Phone: (571)270-1724 , Office: P/2184 )

Most Active Art Unit
2184
Art Unit(s)
2184, 2183
Total Applications
1032
Issued Applications
904
Pending Applications
48
Abandoned Applications
110

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10824750 [patent_doc_number] => 20160170916 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-16 [patent_title] => 'COHERENT MEMORY INTERLEAVING WITH UNIFORM LATENCY' [patent_app_type] => utility [patent_app_number] => 14/568433 [patent_app_country] => US [patent_app_date] => 2014-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4105 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14568433 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/568433
Coherent memory interleaving with uniform latency Dec 11, 2014 Issued
Array ( [id] => 10824761 [patent_doc_number] => 20160170927 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-16 [patent_title] => 'ACCESS AND PROTECTION OF I2C INTERFACES' [patent_app_type] => utility [patent_app_number] => 14/568524 [patent_app_country] => US [patent_app_date] => 2014-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5037 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14568524 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/568524
Access and protection of I2C interfaces Dec 11, 2014 Issued
Array ( [id] => 12194701 [patent_doc_number] => 09898432 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-20 [patent_title] => 'Data transfer control apparatus' [patent_app_type] => utility [patent_app_number] => 14/567287 [patent_app_country] => US [patent_app_date] => 2014-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7445 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14567287 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/567287
Data transfer control apparatus Dec 10, 2014 Issued
Array ( [id] => 12194704 [patent_doc_number] => 09898435 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-20 [patent_title] => 'Aggregate baseboard management controller (BMC) controller' [patent_app_type] => utility [patent_app_number] => 14/566468 [patent_app_country] => US [patent_app_date] => 2014-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6780 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14566468 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/566468
Aggregate baseboard management controller (BMC) controller Dec 9, 2014 Issued
Array ( [id] => 10320745 [patent_doc_number] => 20150205749 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-23 [patent_title] => 'METHODS AND APPARATUS FOR VIRTUAL CHANNEL ALLOCATION VIA A HIGH SPEED BUS INTERFACE' [patent_app_type] => utility [patent_app_number] => 14/566454 [patent_app_country] => US [patent_app_date] => 2014-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8117 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14566454 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/566454
Methods and apparatus for virtual channel allocation via a high speed bus interface Dec 9, 2014 Issued
Array ( [id] => 13240993 [patent_doc_number] => 10133695 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-20 [patent_title] => Link system for establishing high speed network communications and file transfer between hosts using I/O device links [patent_app_type] => utility [patent_app_number] => 14/917402 [patent_app_country] => US [patent_app_date] => 2014-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 19446 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14917402 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/917402
Link system for establishing high speed network communications and file transfer between hosts using I/O device links Dec 7, 2014 Issued
Array ( [id] => 11816911 [patent_doc_number] => 09720861 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-01 [patent_title] => 'Memory access by dual processor systems' [patent_app_type] => utility [patent_app_number] => 14/558147 [patent_app_country] => US [patent_app_date] => 2014-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2666 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14558147 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/558147
Memory access by dual processor systems Dec 1, 2014 Issued
Array ( [id] => 10293174 [patent_doc_number] => 20150178173 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-25 [patent_title] => 'VALIDATING CONNECTION, STRUCTURAL CHARACTERISTICS AND POSITIONING OF CABLE CONNECTORS' [patent_app_type] => utility [patent_app_number] => 14/555824 [patent_app_country] => US [patent_app_date] => 2014-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9720 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14555824 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/555824
Validating connection, structural characteristics and positioning of cable connectors Nov 27, 2014 Issued
Array ( [id] => 11258178 [patent_doc_number] => 09483077 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-01 [patent_title] => 'Charge and data transfer system, apparatus, and method' [patent_app_type] => utility [patent_app_number] => 14/547127 [patent_app_country] => US [patent_app_date] => 2014-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4374 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14547127 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/547127
Charge and data transfer system, apparatus, and method Nov 17, 2014 Issued
Array ( [id] => 11846561 [patent_doc_number] => 09734115 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-15 [patent_title] => 'Memory mapping method and memory mapping system' [patent_app_type] => utility [patent_app_number] => 14/543906 [patent_app_country] => US [patent_app_date] => 2014-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4472 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14543906 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/543906
Memory mapping method and memory mapping system Nov 17, 2014 Issued
Array ( [id] => 10119492 [patent_doc_number] => 09154389 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-10-06 [patent_title] => 'Real-time hierarchical protocol decoding' [patent_app_type] => utility [patent_app_number] => 14/547040 [patent_app_country] => US [patent_app_date] => 2014-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 7916 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14547040 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/547040
Real-time hierarchical protocol decoding Nov 17, 2014 Issued
Array ( [id] => 10264678 [patent_doc_number] => 20150149675 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-28 [patent_title] => 'MEMORY CONTROLLER, INFORMATION PROCESSING APPARATUS, AND METHOD OF CONTROLLING MEMORY CONTROLLER' [patent_app_type] => utility [patent_app_number] => 14/542730 [patent_app_country] => US [patent_app_date] => 2014-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7898 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14542730 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/542730
Memory controller, information processing apparatus, and method of controlling memory controller Nov 16, 2014 Issued
Array ( [id] => 10786176 [patent_doc_number] => 20160132331 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-12 [patent_title] => 'Computer Processor Employing Instruction Block Exit Prediction' [patent_app_type] => utility [patent_app_number] => 14/539087 [patent_app_country] => US [patent_app_date] => 2014-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 30255 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14539087 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/539087
Computer processor employing instruction block exit prediction Nov 11, 2014 Issued
Array ( [id] => 11830771 [patent_doc_number] => 09727513 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-08-08 [patent_title] => 'Unicast packet ready command' [patent_app_type] => utility [patent_app_number] => 14/530760 [patent_app_country] => US [patent_app_date] => 2014-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 23 [patent_no_of_words] => 9723 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14530760 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/530760
Unicast packet ready command Nov 1, 2014 Issued
Array ( [id] => 11482381 [patent_doc_number] => 09588928 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-03-07 [patent_title] => 'Unique packet multicast packet ready command' [patent_app_type] => utility [patent_app_number] => 14/530759 [patent_app_country] => US [patent_app_date] => 2014-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 23 [patent_no_of_words] => 9723 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14530759 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/530759
Unique packet multicast packet ready command Nov 1, 2014 Issued
Array ( [id] => 11830769 [patent_doc_number] => 09727512 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-08-08 [patent_title] => 'Identical packet multicast packet ready command' [patent_app_type] => utility [patent_app_number] => 14/530758 [patent_app_country] => US [patent_app_date] => 2014-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 23 [patent_no_of_words] => 9723 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14530758 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/530758
Identical packet multicast packet ready command Nov 1, 2014 Issued
Array ( [id] => 11700666 [patent_doc_number] => 09690581 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-06-27 [patent_title] => 'Computer processor with deferred operations' [patent_app_type] => utility [patent_app_number] => 14/515033 [patent_app_country] => US [patent_app_date] => 2014-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 10828 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14515033 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/515033
Computer processor with deferred operations Oct 14, 2014 Issued
Array ( [id] => 10764045 [patent_doc_number] => 20160110200 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-21 [patent_title] => 'FLEXIBLE INSTRUCTION EXECUTION IN A PROCESSOR PIPELINE' [patent_app_type] => utility [patent_app_number] => 14/514596 [patent_app_country] => US [patent_app_date] => 2014-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4482 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14514596 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/514596
Flexible instruction execution in a processor pipeline Oct 14, 2014 Issued
Array ( [id] => 10764046 [patent_doc_number] => 20160110201 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-21 [patent_title] => 'FLEXIBLE INSTRUCTION EXECUTION IN A PROCESSOR PIPELINE' [patent_app_type] => utility [patent_app_number] => 14/514708 [patent_app_country] => US [patent_app_date] => 2014-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4350 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14514708 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/514708
Flexible instruction execution in a processor pipeline Oct 14, 2014 Issued
Array ( [id] => 11686584 [patent_doc_number] => 09684631 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-06-20 [patent_title] => 'Processing sytem with a secure set of executable instructions and/or addressing scheme' [patent_app_type] => utility [patent_app_number] => 14/511843 [patent_app_country] => US [patent_app_date] => 2014-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 6038 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14511843 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/511843
Processing sytem with a secure set of executable instructions and/or addressing scheme Oct 9, 2014 Issued
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