Michael Sun

Array ( [id] => 11686584 [patent_doc_number] => 09684631 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-06-20 [patent_title] => 'Processing sytem with a secure set of executable instructions and/or addressing scheme' [patent_app_type] => utility [patent_app_number] => 14/511843 [patent_app_country] => US [patent_app_date] => 2014-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 6038 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14511843 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11614407 [patent_doc_number] => 09652262 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-16 [patent_title] => 'Operation parameter control based upon queued instruction characteristics' [patent_app_type] => utility [patent_app_number] => 14/510440 [patent_app_country] => US [patent_app_date] => 2014-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 9363 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14510440 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10264747 [patent_doc_number] => 20150149744 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-28 [patent_title] => 'DATA PROCESSING APPARATUS AND METHOD FOR PERFORMING VECTOR PROCESSING' [patent_app_type] => utility [patent_app_number] => 14/504947 [patent_app_country] => US [patent_app_date] => 2014-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 10364 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14504947 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10746073 [patent_doc_number] => 20160092224 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-31 [patent_title] => 'CHECKPOINTS FOR A SIMULTANEOUS MULTITHREADING PROCESSOR' [patent_app_type] => utility [patent_app_number] => 14/502229 [patent_app_country] => US [patent_app_date] => 2014-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8416 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14502229 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10746078 [patent_doc_number] => 20160092229 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-31 [patent_title] => 'SYSTEMS AND METHODS FOR MANAGING RETURN STACKS IN A MULTI-THREADED DATA PROCESSING SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/502027 [patent_app_country] => US [patent_app_date] => 2014-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 10437 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14502027 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10746073 [patent_doc_number] => 20160092224 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-31 [patent_title] => 'CHECKPOINTS FOR A SIMULTANEOUS MULTITHREADING PROCESSOR' [patent_app_type] => utility [patent_app_number] => 14/502229 [patent_app_country] => US [patent_app_date] => 2014-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8416 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14502229 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10746063 [patent_doc_number] => 20160092214 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-31 [patent_title] => 'OPTIMIZING GROUPING OF INSTRUCTIONS' [patent_app_type] => utility [patent_app_number] => 14/501578 [patent_app_country] => US [patent_app_date] => 2014-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5384 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14501578 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10015403 [patent_doc_number] => 09058417 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-16 [patent_title] => 'Thread serialization and disablement tool' [patent_app_type] => utility [patent_app_number] => 14/457537 [patent_app_country] => US [patent_app_date] => 2014-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 9212 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14457537 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11027543 [patent_doc_number] => 20160224499 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-04 [patent_title] => 'ONBOARD APPARATUS, AND ONBOARD COMMUNICATION SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/917844 [patent_app_country] => US [patent_app_date] => 2014-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3450 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14917844 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10625510 [patent_doc_number] => 09344470 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-17 [patent_title] => 'Methods and systems for data transmission' [patent_app_type] => utility [patent_app_number] => 14/312542 [patent_app_country] => US [patent_app_date] => 2014-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 34 [patent_no_of_words] => 19551 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14312542 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14123417 [patent_doc_number] => 10248567 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-02 [patent_title] => Cache coherency for direct memory access operations [patent_app_type] => utility [patent_app_number] => 15/319693 [patent_app_country] => US [patent_app_date] => 2014-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 6237 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15319693 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9722944 [patent_doc_number] => 20140258644 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-11 [patent_title] => 'TRANSACTIONAL MEMORY THAT PERFORMS AN ATOMIC METERING COMMAND' [patent_app_type] => utility [patent_app_number] => 14/287012 [patent_app_country] => US [patent_app_date] => 2014-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 50 [patent_figures_cnt] => 50 [patent_no_of_words] => 35848 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14287012 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13143773 [patent_doc_number] => 10089221 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-02 [patent_title] => Systems and methods for memory system management based on information of a memory system [patent_app_type] => utility [patent_app_number] => 14/247833 [patent_app_country] => US [patent_app_date] => 2014-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7311 [patent_no_of_claims] => 59 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14247833 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9774673 [patent_doc_number] => 20140298336 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-02 [patent_title] => 'CENTRAL PROCESSING UNIT, INFORMATION PROCESSING APPARATUS, AND INTRA-VIRTUAL-CORE REGISTER VALUE ACQUISITION METHOD' [patent_app_type] => utility [patent_app_number] => 14/229076 [patent_app_country] => US [patent_app_date] => 2014-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11141 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14229076 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10392908 [patent_doc_number] => 20150277915 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-01 [patent_title] => 'Instruction and Logic for Support of Code Modification' [patent_app_type] => utility [patent_app_number] => 14/229161 [patent_app_country] => US [patent_app_date] => 2014-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 24196 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14229161 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10392904 [patent_doc_number] => 20150277911 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-01 [patent_title] => 'Instruction and Logic for a Logical Move in an Out-Of-Order Processor' [patent_app_type] => utility [patent_app_number] => 14/229179 [patent_app_country] => US [patent_app_date] => 2014-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 22833 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14229179 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10392920 [patent_doc_number] => 20150277926 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-01 [patent_title] => 'Efficient Branch Predictor History Recovery In Pipelined Computer Architectures Employing Branch Prediction And Branch Delay Slots Of Variable Size' [patent_app_type] => utility [patent_app_number] => 14/228436 [patent_app_country] => US [patent_app_date] => 2014-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 21837 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14228436 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10392909 [patent_doc_number] => 20150277916 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-01 [patent_title] => 'METHOD AND APPARATUS FOR IMPLEMENTING A DYNAMIC OUT-OF-ORDER PROCESSOR PIPELINE' [patent_app_type] => utility [patent_app_number] => 14/228690 [patent_app_country] => US [patent_app_date] => 2014-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 15559 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14228690 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10914360 [patent_doc_number] => 20140317379 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-23 [patent_title] => 'INFORMATION PROCESSING SYSTEM, CONTROL APPARATUS, AND METHOD OF CONTROLLING INFORMATION PROCESSING SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/228297 [patent_app_country] => US [patent_app_date] => 2014-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8736 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14228297 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10371779 [patent_doc_number] => 20150256785 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-10 [patent_title] => 'DEVICE CONTROL INTERFACE CABLE AND ASSOCIATED CONTROL SYSTEMS' [patent_app_type] => utility [patent_app_number] => 14/200906 [patent_app_country] => US [patent_app_date] => 2014-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5641 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14200906 [rel_patent_id] =>[rel_patent_doc_number] =>)