Search

Michael Sun

Examiner (ID: 370)

Most Active Art Unit
2184
Art Unit(s)
2184, 2183
Total Applications
1044
Issued Applications
910
Pending Applications
47
Abandoned Applications
111

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11027543 [patent_doc_number] => 20160224499 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-04 [patent_title] => 'ONBOARD APPARATUS, AND ONBOARD COMMUNICATION SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/917844 [patent_app_country] => US [patent_app_date] => 2014-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3450 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14917844 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/917844
Onboard apparatus, and onboard communication system Aug 6, 2014 Issued
Array ( [id] => 10625510 [patent_doc_number] => 09344470 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-17 [patent_title] => 'Methods and systems for data transmission' [patent_app_type] => utility [patent_app_number] => 14/312542 [patent_app_country] => US [patent_app_date] => 2014-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 34 [patent_no_of_words] => 19551 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14312542 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/312542
Methods and systems for data transmission Jun 22, 2014 Issued
Array ( [id] => 14123417 [patent_doc_number] => 10248567 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-02 [patent_title] => Cache coherency for direct memory access operations [patent_app_type] => utility [patent_app_number] => 15/319693 [patent_app_country] => US [patent_app_date] => 2014-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 6237 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15319693 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/319693
Cache coherency for direct memory access operations Jun 15, 2014 Issued
Array ( [id] => 9722944 [patent_doc_number] => 20140258644 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-11 [patent_title] => 'TRANSACTIONAL MEMORY THAT PERFORMS AN ATOMIC METERING COMMAND' [patent_app_type] => utility [patent_app_number] => 14/287012 [patent_app_country] => US [patent_app_date] => 2014-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 50 [patent_figures_cnt] => 50 [patent_no_of_words] => 35848 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14287012 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/287012
Transactional memory that performs an atomic metering command May 23, 2014 Issued
Array ( [id] => 13143773 [patent_doc_number] => 10089221 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-02 [patent_title] => Systems and methods for memory system management based on information of a memory system [patent_app_type] => utility [patent_app_number] => 14/247833 [patent_app_country] => US [patent_app_date] => 2014-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7311 [patent_no_of_claims] => 59 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14247833 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/247833
Systems and methods for memory system management based on information of a memory system Apr 7, 2014 Issued
Array ( [id] => 10392908 [patent_doc_number] => 20150277915 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-01 [patent_title] => 'Instruction and Logic for Support of Code Modification' [patent_app_type] => utility [patent_app_number] => 14/229161 [patent_app_country] => US [patent_app_date] => 2014-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 24196 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14229161 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/229161
Instruction and logic for support of code modification Mar 27, 2014 Issued
Array ( [id] => 10392909 [patent_doc_number] => 20150277916 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-01 [patent_title] => 'METHOD AND APPARATUS FOR IMPLEMENTING A DYNAMIC OUT-OF-ORDER PROCESSOR PIPELINE' [patent_app_type] => utility [patent_app_number] => 14/228690 [patent_app_country] => US [patent_app_date] => 2014-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 15559 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14228690 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/228690
Method and apparatus for implementing a dynamic out-of-order processor pipeline Mar 27, 2014 Issued
Array ( [id] => 9774673 [patent_doc_number] => 20140298336 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-02 [patent_title] => 'CENTRAL PROCESSING UNIT, INFORMATION PROCESSING APPARATUS, AND INTRA-VIRTUAL-CORE REGISTER VALUE ACQUISITION METHOD' [patent_app_type] => utility [patent_app_number] => 14/229076 [patent_app_country] => US [patent_app_date] => 2014-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11141 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14229076 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/229076
Central processing unit, information processing apparatus, and intra-virtual-core register value acquisition method Mar 27, 2014 Issued
Array ( [id] => 10392920 [patent_doc_number] => 20150277926 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-01 [patent_title] => 'Efficient Branch Predictor History Recovery In Pipelined Computer Architectures Employing Branch Prediction And Branch Delay Slots Of Variable Size' [patent_app_type] => utility [patent_app_number] => 14/228436 [patent_app_country] => US [patent_app_date] => 2014-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 21837 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14228436 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/228436
Efficient branch predictor history recovery in pipelined computer architectures employing branch prediction and branch delay slots of variable size Mar 27, 2014 Issued
Array ( [id] => 10914360 [patent_doc_number] => 20140317379 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-23 [patent_title] => 'INFORMATION PROCESSING SYSTEM, CONTROL APPARATUS, AND METHOD OF CONTROLLING INFORMATION PROCESSING SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/228297 [patent_app_country] => US [patent_app_date] => 2014-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8736 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14228297 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/228297
INFORMATION PROCESSING SYSTEM, CONTROL APPARATUS, AND METHOD OF CONTROLLING INFORMATION PROCESSING SYSTEM Mar 27, 2014
Array ( [id] => 10392904 [patent_doc_number] => 20150277911 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-01 [patent_title] => 'Instruction and Logic for a Logical Move in an Out-Of-Order Processor' [patent_app_type] => utility [patent_app_number] => 14/229179 [patent_app_country] => US [patent_app_date] => 2014-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 22833 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14229179 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/229179
Instruction and logic for a logical move in an out-of-order processor Mar 27, 2014 Issued
Array ( [id] => 10371779 [patent_doc_number] => 20150256785 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-10 [patent_title] => 'DEVICE CONTROL INTERFACE CABLE AND ASSOCIATED CONTROL SYSTEMS' [patent_app_type] => utility [patent_app_number] => 14/200906 [patent_app_country] => US [patent_app_date] => 2014-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5641 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14200906 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/200906
Device control interface cable and associated control systems Mar 6, 2014 Issued
Array ( [id] => 9644919 [patent_doc_number] => 20140223032 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-07 [patent_title] => 'MEMORY MODULE STATUS INDICATION' [patent_app_type] => utility [patent_app_number] => 14/173968 [patent_app_country] => US [patent_app_date] => 2014-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4428 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14173968 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/173968
Memory module status indication Feb 5, 2014 Issued
Array ( [id] => 9722868 [patent_doc_number] => 20140258569 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-11 [patent_title] => 'SIGNAL PROCESSING SYSTEM AND ASSOCIATED METHOD' [patent_app_type] => utility [patent_app_number] => 14/173870 [patent_app_country] => US [patent_app_date] => 2014-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 14396 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14173870 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/173870
Signal processing system and associated method Feb 5, 2014 Issued
Array ( [id] => 9658635 [patent_doc_number] => 20140229641 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-14 [patent_title] => 'METHOD AND APPARATUS FOR LATENCY REDUCTION' [patent_app_type] => utility [patent_app_number] => 14/174449 [patent_app_country] => US [patent_app_date] => 2014-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4092 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14174449 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/174449
Method and apparatus for latency reduction Feb 5, 2014 Issued
Array ( [id] => 9479273 [patent_doc_number] => 20140136736 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-15 [patent_title] => 'INFORMATION PROCESSING APPARATUS AND VERIFICATION METHOD' [patent_app_type] => utility [patent_app_number] => 14/156815 [patent_app_country] => US [patent_app_date] => 2014-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 13619 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14156815 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/156815
INFORMATION PROCESSING APPARATUS AND VERIFICATION METHOD Jan 15, 2014 Abandoned
Array ( [id] => 10268967 [patent_doc_number] => 20150153964 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-04 [patent_title] => 'PLACING A STORAGE NETWORK DEVICE INTO A MAINTENANCE MODE IN A VIRTUALIZED COMPUTING ENVIRONMENT' [patent_app_type] => utility [patent_app_number] => 14/156480 [patent_app_country] => US [patent_app_date] => 2014-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5779 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14156480 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/156480
Placing a storage network device into a maintenance mode in a virtualized computing environment Jan 15, 2014 Issued
Array ( [id] => 9722862 [patent_doc_number] => 20140258563 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-11 [patent_title] => 'MEMORY CARD CONTROLLER AND HOST DEVICE INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/155820 [patent_app_country] => US [patent_app_date] => 2014-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4731 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14155820 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/155820
Memory card controller and host device including the same Jan 14, 2014 Issued
Array ( [id] => 9980366 [patent_doc_number] => 09026696 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-05-05 [patent_title] => 'Using I/O track information for continuous push with splitter for storage device' [patent_app_type] => utility [patent_app_number] => 14/152126 [patent_app_country] => US [patent_app_date] => 2014-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 46 [patent_no_of_words] => 21993 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14152126 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/152126
Using I/O track information for continuous push with splitter for storage device Jan 9, 2014 Issued
Array ( [id] => 9961140 [patent_doc_number] => 09009364 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-04-14 [patent_title] => 'Apparatus and method for accelerated page link list processing in a packet processor operating at wirespeed' [patent_app_type] => utility [patent_app_number] => 14/142643 [patent_app_country] => US [patent_app_date] => 2013-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3824 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14142643 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/142643
Apparatus and method for accelerated page link list processing in a packet processor operating at wirespeed Dec 26, 2013 Issued
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