Michael Sun

Array ( [id] => 8976820 [patent_doc_number] => 20130210250 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-15 [patent_title] => 'CONVERTER AND PROGRAM' [patent_app_type] => utility [patent_app_number] => 13/760463 [patent_app_country] => US [patent_app_date] => 2013-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 12821 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13760463 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8991802 [patent_doc_number] => 20130219083 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-22 [patent_title] => 'PERIPHERAL DEVICE, INFORMATION PROCESSING SYSTEM, CONTROL METHOD, AND STORAGE MEDIUM' [patent_app_type] => utility [patent_app_number] => 13/754965 [patent_app_country] => US [patent_app_date] => 2013-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7272 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13754965 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9070956 [patent_doc_number] => 20130262712 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-03 [patent_title] => 'ELECTRONIC DEVICE AND METHOD OF SIGNAL TRANSMISSION THEREIN' [patent_app_type] => utility [patent_app_number] => 13/755736 [patent_app_country] => US [patent_app_date] => 2013-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4682 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13755736 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9636990 [patent_doc_number] => 20140215099 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-31 [patent_title] => 'Systems and Methods for Providing a Wireless Computer Control Link' [patent_app_type] => utility [patent_app_number] => 13/755721 [patent_app_country] => US [patent_app_date] => 2013-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4267 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13755721 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9044026 [patent_doc_number] => 20130246664 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-19 [patent_title] => 'REMOTE CONTROL METHOD, SYSTEM AND ASSOCIATED APPARATUS FOR SMART TV' [patent_app_type] => utility [patent_app_number] => 13/753696 [patent_app_country] => US [patent_app_date] => 2013-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4648 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13753696 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11775068 [patent_doc_number] => 09383995 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-07-05 [patent_title] => 'Load ordering in a weakly-ordered processor' [patent_app_type] => utility [patent_app_number] => 13/750972 [patent_app_country] => US [patent_app_date] => 2013-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 7315 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13750972 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9044107 [patent_doc_number] => 20130246745 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-19 [patent_title] => 'VECTOR PROCESSOR AND VECTOR PROCESSOR PROCESSING METHOD' [patent_app_type] => utility [patent_app_number] => 13/733524 [patent_app_country] => US [patent_app_date] => 2013-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 11984 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13733524 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9571608 [patent_doc_number] => 20140189321 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-03 [patent_title] => 'INSTRUCTIONS AND LOGIC TO VECTORIZE CONDITIONAL LOOPS' [patent_app_type] => utility [patent_app_number] => 13/731809 [patent_app_country] => US [patent_app_date] => 2012-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 18892 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13731809 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9571598 [patent_doc_number] => 20140189311 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-03 [patent_title] => 'SYSTEM AND METHOD FOR PERFORMING A SHUFFLE INSTRUCTION' [patent_app_type] => utility [patent_app_number] => 13/732243 [patent_app_country] => US [patent_app_date] => 2012-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4195 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13732243 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9571605 [patent_doc_number] => 20140189318 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-03 [patent_title] => 'AUTOMATIC REGISTER PORT SELECTION IN EXTENSIBLE PROCESSOR ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 13/732183 [patent_app_country] => US [patent_app_date] => 2012-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 12253 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13732183 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9571592 [patent_doc_number] => 20140189305 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-03 [patent_title] => 'REDUNDANT EXECUTION FOR RELIABILITY IN A SUPER FMA ALU' [patent_app_type] => utility [patent_app_number] => 13/732228 [patent_app_country] => US [patent_app_date] => 2012-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5174 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13732228 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9571591 [patent_doc_number] => 20140189304 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-03 [patent_title] => 'BIT-LEVEL REGISTER FILE UPDATES IN EXTENSIBLE PROCESSOR ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 13/732155 [patent_app_country] => US [patent_app_date] => 2012-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 12133 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13732155 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9571473 [patent_doc_number] => 20140189186 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-03 [patent_title] => 'MEMORY BUS ATTACHED INPUT/OUTPUT (\'I/O\') SUBSYSTEM MANAGEMENT IN A COMPUTING SYSTEM' [patent_app_type] => utility [patent_app_number] => 13/729496 [patent_app_country] => US [patent_app_date] => 2012-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6381 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13729496 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9571451 [patent_doc_number] => 20140189164 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-03 [patent_title] => 'MEMORY BUS ATTACHED INPUT/OUTPUT (\'I/O\') SUBSYSTEM MANAGEMENT IN A COMPUTING SYSTEM' [patent_app_type] => utility [patent_app_number] => 13/729599 [patent_app_country] => US [patent_app_date] => 2012-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6411 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13729599 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8978905 [patent_doc_number] => 20130212336 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-15 [patent_title] => 'Method and Apparatus for Memory Write Performance Optimization in Architectures with Out-of-Order Read/Request-for-Ownership Response' [patent_app_type] => utility [patent_app_number] => 13/727532 [patent_app_country] => US [patent_app_date] => 2012-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3368 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13727532 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8978905 [patent_doc_number] => 20130212336 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-15 [patent_title] => 'Method and Apparatus for Memory Write Performance Optimization in Architectures with Out-of-Order Read/Request-for-Ownership Response' [patent_app_type] => utility [patent_app_number] => 13/727532 [patent_app_country] => US [patent_app_date] => 2012-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3368 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13727532 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8929081 [patent_doc_number] => 20130184842 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-07-18 [patent_title] => 'INCREASED SPEED OF PROCESSING OF DATA RECEIVED OVER A COMMUNICATIONS LINK' [patent_app_type] => utility [patent_app_number] => 13/717505 [patent_app_country] => US [patent_app_date] => 2012-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2880 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13717505 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9592734 [patent_doc_number] => 08782300 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-15 [patent_title] => 'Electronic apparatus' [patent_app_type] => utility [patent_app_number] => 13/692506 [patent_app_country] => US [patent_app_date] => 2012-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 19 [patent_no_of_words] => 12165 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13692506 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9592733 [patent_doc_number] => 08782298 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-15 [patent_title] => 'Computing device and method for adjusting physical links of a SAS expander of the computing device' [patent_app_type] => utility [patent_app_number] => 13/691907 [patent_app_country] => US [patent_app_date] => 2012-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3459 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13691907 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8855458 [patent_doc_number] => 20130145133 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-06 [patent_title] => 'PROCESSOR, APPARATUS AND METHOD FOR GENERATING INSTRUCTIONS' [patent_app_type] => utility [patent_app_number] => 13/690079 [patent_app_country] => US [patent_app_date] => 2012-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3956 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13690079 [rel_patent_id] =>[rel_patent_doc_number] =>)