Search

Michael Sun

Examiner (ID: 3584, Phone: (571)270-1724 , Office: P/2184 )

Most Active Art Unit
2184
Art Unit(s)
2184, 2183
Total Applications
1043
Issued Applications
909
Pending Applications
50
Abandoned Applications
111

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18847092 [patent_doc_number] => 20230409496 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => MEMORY DEVICE SUPPORTING A HIGH-EFFICIENT INPUT/OUTPUT INTERFACE AND A MEMORY SYSTEM INCLUDING THE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/242034 [patent_app_country] => US [patent_app_date] => 2023-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18700 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18242034 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/242034
Memory device supporting a high-efficient input/output interface and a memory system including the memory device Sep 4, 2023 Issued
Array ( [id] => 18864166 [patent_doc_number] => 20230418602 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-28 [patent_title] => SYSTEMS, APPARATUSES, AND METHODS FOR ADDITION OF PARTIAL PRODUCTS [patent_app_type] => utility [patent_app_number] => 18/456699 [patent_app_country] => US [patent_app_date] => 2023-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19670 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 328 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18456699 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/456699
Systems, apparatuses, and methods for addition of partial products Aug 27, 2023 Issued
Array ( [id] => 19725909 [patent_doc_number] => 20250028660 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-23 [patent_title] => MEMORY MODULE WITH TIMING-CONTROLLED DATA BUFFERING [patent_app_type] => utility [patent_app_number] => 18/452554 [patent_app_country] => US [patent_app_date] => 2023-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11206 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18452554 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/452554
MEMORY MODULE WITH TIMING-CONTROLLED DATA BUFFERING Aug 19, 2023 Pending
Array ( [id] => 19787394 [patent_doc_number] => 20250061073 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-20 [patent_title] => Interrupt Latency Resilient UART Driver [patent_app_type] => utility [patent_app_number] => 18/235071 [patent_app_country] => US [patent_app_date] => 2023-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6429 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18235071 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/235071
Interrupt latency resilient UART driver Aug 16, 2023 Issued
Array ( [id] => 19228279 [patent_doc_number] => 12007915 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-06-11 [patent_title] => Field programmable gate array-based low latency disaggregated system orchestrator [patent_app_type] => utility [patent_app_number] => 18/447707 [patent_app_country] => US [patent_app_date] => 2023-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5337 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18447707 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/447707
Field programmable gate array-based low latency disaggregated system orchestrator Aug 9, 2023 Issued
Array ( [id] => 19978773 [patent_doc_number] => 12346248 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-01 [patent_title] => Private memory mode sequential memory access in multi-threaded computing [patent_app_type] => utility [patent_app_number] => 18/231820 [patent_app_country] => US [patent_app_date] => 2023-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 15486 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18231820 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/231820
Private memory mode sequential memory access in multi-threaded computing Aug 8, 2023 Issued
Array ( [id] => 20174784 [patent_doc_number] => 12393531 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-19 [patent_title] => Quad-channel DRAM [patent_app_type] => utility [patent_app_number] => 18/231108 [patent_app_country] => US [patent_app_date] => 2023-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 4931 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18231108 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/231108
Quad-channel DRAM Aug 6, 2023 Issued
Array ( [id] => 18941731 [patent_doc_number] => 20240036870 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-01 [patent_title] => Coprocessor Operation Bundling [patent_app_type] => utility [patent_app_number] => 18/361212 [patent_app_country] => US [patent_app_date] => 2023-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14007 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18361212 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/361212
Coprocessor operation bundling Jul 27, 2023 Issued
Array ( [id] => 19204764 [patent_doc_number] => 20240176663 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => TENSOR MAP CACHE STORAGE [patent_app_type] => utility [patent_app_number] => 18/219622 [patent_app_country] => US [patent_app_date] => 2023-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 79877 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18219622 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/219622
TENSOR MAP CACHE STORAGE Jul 6, 2023 Pending
Array ( [id] => 19811006 [patent_doc_number] => 12242398 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-04 [patent_title] => Polling regulation for storage input/output in a computer system [patent_app_type] => utility [patent_app_number] => 18/348880 [patent_app_country] => US [patent_app_date] => 2023-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5861 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18348880 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/348880
Polling regulation for storage input/output in a computer system Jul 6, 2023 Issued
Array ( [id] => 18741832 [patent_doc_number] => 20230350813 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => Method and Apparatus for Dual Issue Multiply Instructions [patent_app_type] => utility [patent_app_number] => 18/348047 [patent_app_country] => US [patent_app_date] => 2023-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 38428 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18348047 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/348047
Method and apparatus for dual issue multiply instructions Jul 5, 2023 Issued
Array ( [id] => 18904641 [patent_doc_number] => 20240020126 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-18 [patent_title] => Fusion with Destructive Instructions [patent_app_type] => utility [patent_app_number] => 18/344986 [patent_app_country] => US [patent_app_date] => 2023-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12443 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18344986 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/344986
Fusion with destructive instructions Jun 29, 2023 Issued
Array ( [id] => 18741837 [patent_doc_number] => 20230350819 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => METHODS AND APPARATUS TO EXTEND LOCAL BUFFER OF A HARDWARE ACCELERATOR [patent_app_type] => utility [patent_app_number] => 18/345098 [patent_app_country] => US [patent_app_date] => 2023-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14203 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18345098 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/345098
Methods and apparatus to extend local buffer of a hardware accelerator Jun 29, 2023 Issued
Array ( [id] => 19413326 [patent_doc_number] => 12079142 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-03 [patent_title] => PC-based instruction group permissions [patent_app_type] => utility [patent_app_number] => 18/343145 [patent_app_country] => US [patent_app_date] => 2023-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 21 [patent_no_of_words] => 18340 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18343145 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/343145
PC-based instruction group permissions Jun 27, 2023 Issued
Array ( [id] => 20160031 [patent_doc_number] => 12386659 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-12 [patent_title] => Scheduling multiple processing-in-memory (PIM) threads and non-PIM threads [patent_app_type] => utility [patent_app_number] => 18/214733 [patent_app_country] => US [patent_app_date] => 2023-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8009 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18214733 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/214733
Scheduling multiple processing-in-memory (PIM) threads and non-PIM threads Jun 26, 2023 Issued
Array ( [id] => 18864339 [patent_doc_number] => 20230418775 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-28 [patent_title] => Heterogeneous Compute Platform Architecture For Efficient Hosting Of Network Functions [patent_app_type] => utility [patent_app_number] => 18/213028 [patent_app_country] => US [patent_app_date] => 2023-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5963 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18213028 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/213028
Heterogeneous compute platform architecture for efficient hosting of network functions Jun 21, 2023 Issued
Array ( [id] => 19765032 [patent_doc_number] => 12223323 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-11 [patent_title] => Out-of-order vector iota calculations [patent_app_type] => utility [patent_app_number] => 18/337652 [patent_app_country] => US [patent_app_date] => 2023-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8260 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18337652 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/337652
Out-of-order vector iota calculations Jun 19, 2023 Issued
Array ( [id] => 18941726 [patent_doc_number] => 20240036865 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-01 [patent_title] => APPARATUSES, METHODS, AND SYSTEMS FOR HASHING INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 18/336985 [patent_app_country] => US [patent_app_date] => 2023-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 29197 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18336985 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/336985
Apparatuses, methods, and systems for hashing instructions Jun 16, 2023 Issued
Array ( [id] => 19603224 [patent_doc_number] => 20240394104 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => PRESERVING QUALITY OF SERVICE FOR CLIENT APPLICATIONS HAVING WORKLOADS FOR EXECUTION BY A COMPUTE CORE OR A HARDWARE ACCELERATOR [patent_app_type] => utility [patent_app_number] => 18/324693 [patent_app_country] => US [patent_app_date] => 2023-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12359 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18324693 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/324693
Preserving quality of service for client applications having workloads for execution by a compute core or a hardware accelerator May 25, 2023 Issued
Array ( [id] => 19933579 [patent_doc_number] => 12306783 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-20 [patent_title] => Top level network and array level network for reconfigurable data processors [patent_app_type] => utility [patent_app_number] => 18/199361 [patent_app_country] => US [patent_app_date] => 2023-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 24 [patent_no_of_words] => 14457 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18199361 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/199361
Top level network and array level network for reconfigurable data processors May 17, 2023 Issued
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