Search

Michael Thanh Tran

Examiner (ID: 2981, Phone: (571)272-1795 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2827, 2511, 2818
Total Applications
3089
Issued Applications
2919
Pending Applications
108
Abandoned Applications
104

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 661176 [patent_doc_number] => 07106655 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-12 [patent_title] => 'Multi-phase clock signal generator and method having inherently unlimited frequency capability' [patent_app_type] => utility [patent_app_number] => 11/027376 [patent_app_country] => US [patent_app_date] => 2004-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 5908 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/106/07106655.pdf [firstpage_image] =>[orig_patent_app_number] => 11027376 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/027376
Multi-phase clock signal generator and method having inherently unlimited frequency capability Dec 28, 2004 Issued
Array ( [id] => 834789 [patent_doc_number] => 07397696 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-07-08 [patent_title] => 'Current sensing architecture for high bitline voltage, rail to rail output swing and Vcc noise cancellation' [patent_app_type] => utility [patent_app_number] => 11/023914 [patent_app_country] => US [patent_app_date] => 2004-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 10450 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/397/07397696.pdf [firstpage_image] =>[orig_patent_app_number] => 11023914 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/023914
Current sensing architecture for high bitline voltage, rail to rail output swing and Vcc noise cancellation Dec 27, 2004 Issued
Array ( [id] => 5806378 [patent_doc_number] => 20060092731 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-04 [patent_title] => 'Semiconductor memory device for low power system' [patent_app_type] => utility [patent_app_number] => 11/025800 [patent_app_country] => US [patent_app_date] => 2004-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 13035 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0092/20060092731.pdf [firstpage_image] =>[orig_patent_app_number] => 11025800 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/025800
Semiconductor memory device for low power system Dec 27, 2004 Issued
Array ( [id] => 5612791 [patent_doc_number] => 20060114719 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-01 [patent_title] => 'Novel combination nonvolatile integrated memory system using a universal technology most suitable for high-density, high-flexibility and high-security sim-card, smart-card and e-passport applications' [patent_app_type] => utility [patent_app_number] => 11/025822 [patent_app_country] => US [patent_app_date] => 2004-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 17869 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0114/20060114719.pdf [firstpage_image] =>[orig_patent_app_number] => 11025822 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/025822
Combination nonvolatile integrated memory system using a universal technology most suitable for high-density, high-flexibility and high-security sim-card, smart-card and e-passport applications Dec 23, 2004 Issued
Array ( [id] => 7073710 [patent_doc_number] => 20050146977 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-07 [patent_title] => 'Circuit' [patent_app_type] => utility [patent_app_number] => 11/009967 [patent_app_country] => US [patent_app_date] => 2004-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3723 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0146/20050146977.pdf [firstpage_image] =>[orig_patent_app_number] => 11009967 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/009967
Circuit Dec 9, 2004 Issued
Array ( [id] => 7225754 [patent_doc_number] => 20050078515 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-14 [patent_title] => 'Non-volatile memory with test rows for disturb detection' [patent_app_type] => utility [patent_app_number] => 11/004069 [patent_app_country] => US [patent_app_date] => 2004-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4400 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0078/20050078515.pdf [firstpage_image] =>[orig_patent_app_number] => 11004069 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/004069
Non-volatile memory with test rows for disturb detection Dec 2, 2004 Issued
Array ( [id] => 5099925 [patent_doc_number] => 20070183186 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-09 [patent_title] => 'Mram based on vertical current writing and its control method' [patent_app_type] => utility [patent_app_number] => 10/599514 [patent_app_country] => US [patent_app_date] => 2004-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4171 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0183/20070183186.pdf [firstpage_image] =>[orig_patent_app_number] => 10599514 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/599514
MRAM based on vertical current writing and its control method Nov 30, 2004 Issued
Array ( [id] => 7243534 [patent_doc_number] => 20050140969 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-30 [patent_title] => 'Semiconductor memory device for reducing current consumption in operation' [patent_app_type] => utility [patent_app_number] => 10/998678 [patent_app_country] => US [patent_app_date] => 2004-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3789 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20050140969.pdf [firstpage_image] =>[orig_patent_app_number] => 10998678 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/998678
Semiconductor memory device for reducing current consumption in operation Nov 29, 2004 Issued
Array ( [id] => 710571 [patent_doc_number] => 07061819 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-13 [patent_title] => 'Memory device' [patent_app_type] => utility [patent_app_number] => 10/995396 [patent_app_country] => US [patent_app_date] => 2004-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 4917 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/061/07061819.pdf [firstpage_image] =>[orig_patent_app_number] => 10995396 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/995396
Memory device Nov 23, 2004 Issued
Array ( [id] => 652271 [patent_doc_number] => 07113446 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-26 [patent_title] => 'Latch circuit and synchronous memory including the same' [patent_app_type] => utility [patent_app_number] => 10/995528 [patent_app_country] => US [patent_app_date] => 2004-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 7907 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/113/07113446.pdf [firstpage_image] =>[orig_patent_app_number] => 10995528 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/995528
Latch circuit and synchronous memory including the same Nov 23, 2004 Issued
Array ( [id] => 6937721 [patent_doc_number] => 20050111282 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-26 [patent_title] => 'Semiconductor memory device with refreshment control' [patent_app_type] => utility [patent_app_number] => 10/997320 [patent_app_country] => US [patent_app_date] => 2004-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 9939 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0111/20050111282.pdf [firstpage_image] =>[orig_patent_app_number] => 10997320 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/997320
Semiconductor memory device with refreshment control Nov 23, 2004 Issued
Array ( [id] => 6924565 [patent_doc_number] => 20050237820 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-27 [patent_title] => 'Semiconductor integrated circuit device' [patent_app_type] => utility [patent_app_number] => 10/995198 [patent_app_country] => US [patent_app_date] => 2004-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 14552 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0237/20050237820.pdf [firstpage_image] =>[orig_patent_app_number] => 10995198 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/995198
Semiconductor integrated circuit device Nov 23, 2004 Issued
Array ( [id] => 554614 [patent_doc_number] => 07167411 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-23 [patent_title] => 'Apparatus for testing a nonvolatile memory and a method thereof' [patent_app_type] => utility [patent_app_number] => 10/996708 [patent_app_country] => US [patent_app_date] => 2004-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3583 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/167/07167411.pdf [firstpage_image] =>[orig_patent_app_number] => 10996708 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/996708
Apparatus for testing a nonvolatile memory and a method thereof Nov 23, 2004 Issued
Array ( [id] => 745525 [patent_doc_number] => 07031181 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-04-18 [patent_title] => 'Multi-pulse reset write scheme for phase-change memories' [patent_app_type] => utility [patent_app_number] => 10/995644 [patent_app_country] => US [patent_app_date] => 2004-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3531 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/031/07031181.pdf [firstpage_image] =>[orig_patent_app_number] => 10995644 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/995644
Multi-pulse reset write scheme for phase-change memories Nov 22, 2004 Issued
Array ( [id] => 594636 [patent_doc_number] => 07443747 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-28 [patent_title] => 'Memory array bit line coupling capacitor cancellation' [patent_app_type] => utility [patent_app_number] => 10/997708 [patent_app_country] => US [patent_app_date] => 2004-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2791 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/443/07443747.pdf [firstpage_image] =>[orig_patent_app_number] => 10997708 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/997708
Memory array bit line coupling capacitor cancellation Nov 22, 2004 Issued
Array ( [id] => 543264 [patent_doc_number] => 07180822 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-20 [patent_title] => 'Semiconductor memory device without decreasing performance thereof even if refresh operation or word line changing operation occur during burst operation' [patent_app_type] => utility [patent_app_number] => 10/994632 [patent_app_country] => US [patent_app_date] => 2004-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4933 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/180/07180822.pdf [firstpage_image] =>[orig_patent_app_number] => 10994632 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/994632
Semiconductor memory device without decreasing performance thereof even if refresh operation or word line changing operation occur during burst operation Nov 22, 2004 Issued
Array ( [id] => 545292 [patent_doc_number] => 07173865 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-02-06 [patent_title] => 'Stacked die memory depth expansion' [patent_app_type] => utility [patent_app_number] => 10/996018 [patent_app_country] => US [patent_app_date] => 2004-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4321 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/173/07173865.pdf [firstpage_image] =>[orig_patent_app_number] => 10996018 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/996018
Stacked die memory depth expansion Nov 21, 2004 Issued
Array ( [id] => 674414 [patent_doc_number] => 07092280 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-15 [patent_title] => 'SRAM with dynamically asymmetric cell' [patent_app_type] => utility [patent_app_number] => 10/996284 [patent_app_country] => US [patent_app_date] => 2004-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3396 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/092/07092280.pdf [firstpage_image] =>[orig_patent_app_number] => 10996284 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/996284
SRAM with dynamically asymmetric cell Nov 21, 2004 Issued
Array ( [id] => 7247435 [patent_doc_number] => 20050073898 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-07 [patent_title] => 'Apparatus and method for disturb-free programming of passive element memory cells' [patent_app_type] => utility [patent_app_number] => 10/994016 [patent_app_country] => US [patent_app_date] => 2004-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7252 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0073/20050073898.pdf [firstpage_image] =>[orig_patent_app_number] => 10994016 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/994016
Apparatus and method for disturb-free programming of passive element memory cells Nov 18, 2004 Issued
Array ( [id] => 5746800 [patent_doc_number] => 20060109731 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-25 [patent_title] => 'Twin-cell bit line sensing configuration' [patent_app_type] => utility [patent_app_number] => 10/992826 [patent_app_country] => US [patent_app_date] => 2004-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3174 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20060109731.pdf [firstpage_image] =>[orig_patent_app_number] => 10992826 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/992826
Twin-cell bit line sensing configuration Nov 18, 2004 Issued
Menu