Michael Thanh Tran

Array ( [id] => 728086 [patent_doc_number] => 07046542 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-16 [patent_title] => 'Semiconductor integrated circuit device' [patent_app_type] => utility [patent_app_number] => 10/875307 [patent_app_country] => US [patent_app_date] => 2004-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 2997 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/046/07046542.pdf [firstpage_image] =>[orig_patent_app_number] => 10875307 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 718934 [patent_doc_number] => 07054210 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-30 [patent_title] => 'Write/precharge flag signal generation circuit and circuit for driving bit line isolation circuit in sense amplifier using the same' [patent_app_type] => utility [patent_app_number] => 10/876158 [patent_app_country] => US [patent_app_date] => 2004-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3568 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/054/07054210.pdf [firstpage_image] =>[orig_patent_app_number] => 10876158 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 714012 [patent_doc_number] => 07057951 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-06 [patent_title] => 'Semiconductor memory device for controlling write recovery time' [patent_app_type] => utility [patent_app_number] => 10/877038 [patent_app_country] => US [patent_app_date] => 2004-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4103 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/057/07057951.pdf [firstpage_image] =>[orig_patent_app_number] => 10877038 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 728176 [patent_doc_number] => 07046575 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-16 [patent_title] => 'Bus connection circuit for read operation of multi-port memory device' [patent_app_type] => utility [patent_app_number] => 10/876504 [patent_app_country] => US [patent_app_date] => 2004-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6735 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/046/07046575.pdf [firstpage_image] =>[orig_patent_app_number] => 10876504 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 409866 [patent_doc_number] => 07286378 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-23 [patent_title] => 'Serial transistor-cell array architecture' [patent_app_type] => utility [patent_app_number] => 10/873112 [patent_app_country] => US [patent_app_date] => 2004-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5843 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/286/07286378.pdf [firstpage_image] =>[orig_patent_app_number] => 10873112 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 554476 [patent_doc_number] => 07167400 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-23 [patent_title] => 'Apparatus and method for improving dynamic refresh in a memory device' [patent_app_type] => utility [patent_app_number] => 10/873968 [patent_app_country] => US [patent_app_date] => 2004-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 4502 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/167/07167400.pdf [firstpage_image] =>[orig_patent_app_number] => 10873968 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 728183 [patent_doc_number] => 07046579 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-16 [patent_title] => 'Semiconductor storage device' [patent_app_type] => utility [patent_app_number] => 10/872570 [patent_app_country] => US [patent_app_date] => 2004-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 22 [patent_no_of_words] => 8396 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/046/07046579.pdf [firstpage_image] =>[orig_patent_app_number] => 10872570 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7414071 [patent_doc_number] => 20040228194 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-18 [patent_title] => 'Nonvolatile semiconductor memory and read method' [patent_app_type] => new [patent_app_number] => 10/872507 [patent_app_country] => US [patent_app_date] => 2004-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 13991 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 307 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0228/20040228194.pdf [firstpage_image] =>[orig_patent_app_number] => 10872507 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 395124 [patent_doc_number] => 07298653 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-11-20 [patent_title] => 'Reducing cross die variability in an EEPROM array' [patent_app_type] => utility [patent_app_number] => 10/873872 [patent_app_country] => US [patent_app_date] => 2004-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 3747 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/298/07298653.pdf [firstpage_image] =>[orig_patent_app_number] => 10873872 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 647700 [patent_doc_number] => 07120048 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-10 [patent_title] => 'Nonvolatile memory vertical ring bit and write-read structure' [patent_app_type] => utility [patent_app_number] => 10/874132 [patent_app_country] => US [patent_app_date] => 2004-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 9919 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/120/07120048.pdf [firstpage_image] =>[orig_patent_app_number] => 10874132 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 644088 [patent_doc_number] => 07123506 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-17 [patent_title] => 'Method and system for performing more consistent switching of magnetic elements in a magnetic memory' [patent_app_type] => utility [patent_app_number] => 10/860902 [patent_app_country] => US [patent_app_date] => 2004-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 4929 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/123/07123506.pdf [firstpage_image] =>[orig_patent_app_number] => 10860902 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 780903 [patent_doc_number] => 06996011 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-02-07 [patent_title] => 'NAND-type non-volatile memory cell and method for operating same' [patent_app_type] => utility [patent_app_number] => 10/855286 [patent_app_country] => US [patent_app_date] => 2004-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 24 [patent_no_of_words] => 10867 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/996/06996011.pdf [firstpage_image] =>[orig_patent_app_number] => 10855286 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7059878 [patent_doc_number] => 20050002238 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-06 [patent_title] => 'Semiconductor memory device and method of controlling the same' [patent_app_type] => utility [patent_app_number] => 10/852288 [patent_app_country] => US [patent_app_date] => 2004-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 3038 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20050002238.pdf [firstpage_image] =>[orig_patent_app_number] => 10852288 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7300343 [patent_doc_number] => 20040215902 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-28 [patent_title] => 'Memory access interface for a micro-controller system with address/data multiplexing bus' [patent_app_type] => new [patent_app_number] => 10/852169 [patent_app_country] => US [patent_app_date] => 2004-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1592 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0215/20040215902.pdf [firstpage_image] =>[orig_patent_app_number] => 10852169 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1010456 [patent_doc_number] => 06901023 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-31 [patent_title] => 'Word line driver for negative voltage' [patent_app_type] => utility [patent_app_number] => 10/852899 [patent_app_country] => US [patent_app_date] => 2004-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5869 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/901/06901023.pdf [firstpage_image] =>[orig_patent_app_number] => 10852899 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7274276 [patent_doc_number] => 20040233727 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-25 [patent_title] => 'Programming verification method of nonvolatile memory cell, semiconductor memory device, and portable electronic apparatus having the semiconductor memory device' [patent_app_type] => new [patent_app_number] => 10/848614 [patent_app_country] => US [patent_app_date] => 2004-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 22924 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0233/20040233727.pdf [firstpage_image] =>[orig_patent_app_number] => 10848614 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7608823 [patent_doc_number] => 06999368 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-02-14 [patent_title] => 'Semiconductor memory device and semiconductor integrated circuit device' [patent_app_type] => utility [patent_app_number] => 10/847392 [patent_app_country] => US [patent_app_date] => 2004-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7659 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/999/06999368.pdf [firstpage_image] =>[orig_patent_app_number] => 10847392 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7220376 [patent_doc_number] => 20050254282 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-17 [patent_title] => 'REFERENCE GENERATOR SYSTEM AND METHODS FOR READING FERROELECTRIC MEMORY CELLS USING REDUCED BITLINE VOLTAGES' [patent_app_type] => utility [patent_app_number] => 10/847412 [patent_app_country] => US [patent_app_date] => 2004-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 9964 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0254/20050254282.pdf [firstpage_image] =>[orig_patent_app_number] => 10847412 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 982637 [patent_doc_number] => 06927481 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-09 [patent_title] => 'Leadframe inductors' [patent_app_type] => utility [patent_app_number] => 10/846905 [patent_app_country] => US [patent_app_date] => 2004-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2678 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/927/06927481.pdf [firstpage_image] =>[orig_patent_app_number] => 10846905 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 944812 [patent_doc_number] => 06967868 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-11-22 [patent_title] => 'Semiconductor memory device having flexible column redundancy scheme' [patent_app_type] => utility [patent_app_number] => 10/845314 [patent_app_country] => US [patent_app_date] => 2004-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 8494 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/967/06967868.pdf [firstpage_image] =>[orig_patent_app_number] => 10845314 [rel_patent_id] =>[rel_patent_doc_number] =>)